| /Zephyr-latest/drivers/modem/ |
| D | Kconfig.hl7800 | 26 default 30
79 bool "Band 1 (2000MHz)"
82 Enable Band 1 (2000MHz)
85 bool "Band 2 (1900MHz)"
88 Enable Band 2 (1900MHz)
91 bool "Band 3 (1800MHz)"
94 Enable Band 3 (1800MHz)
97 bool "Band 4 (1700MHz)"
100 Enable Band 4 (1700MHz)
103 bool "Band 5 (850MHz)"
[all …]
|
| /Zephyr-latest/soc/sifive/sifive_freedom/fu700/ |
| D | clock.c | 13 BUILD_ASSERT(MHZ(1000) == DT_PROP(DT_NODELABEL(coreclk), clock_frequency),
26 * - core: to 1GHz PLL (CORE_PLL) from 26MHz oscillator (HFCLK)
27 * - peri: to 250MHz PLL (HFPCLKPLL) from HFCLK
28 * - ddr: to 923MHz PLL (DDRPLL) from HFCLK (half of the data rate)
31 * Note: Valid PLL VCO range is 2400MHz to 4800MHz
37 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
38 PLL_F(76) | /* VCO: 2 x (76 + 1) = 154 = 4004MHz */ in soc_early_init_hook()
39 PLL_Q(2) | /* output divider: VCO / 2^2 = 1001MHz */ in soc_early_init_hook()
40 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in soc_early_init_hook()
52 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
[all …]
|
| /Zephyr-latest/dts/bindings/i3c/ |
| D | nuvoton,npcx-i3c.yaml | 11 clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
12 core-prescaler = <3>; /* CORE_CLK runs at 30MHz */
13 apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
14 apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
15 apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
16 apb4-prescaler = <3>; /* APB4_CLK runs at 30MHz */
|
| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | wch,afio.yaml | 41 default: "max-speed-2mhz"
43 - "max-speed-10mhz"
44 - "max-speed-2mhz"
45 - "max-speed-30mhz"
|
| /Zephyr-latest/tests/drivers/flash/common/boards/ |
| D | nrf52840dk_spi_nor_wp_hold.overlay | 42 spi-max-frequency = <8000000>; // chip supports 80Mhz, SPI0 supports 8MHz
54 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
|
| D | nrf52840dk_spi_nor.overlay | 42 spi-max-frequency = <8000000>; // chip supports 80Mhz, SPI0 supports 8MHz
52 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/ |
| D | pll_hsi_240.overlay | 14 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
20 mul-n = <30>;
|
| /Zephyr-latest/soc/snps/nsim/arc_classic/hs/ |
| D | Kconfig.defconfig.hs6x_smp | 15 default 30
18 # SMP simulation is slower than single core, 1 Mhz seems reasonable match with wallclock
|
| /Zephyr-latest/dts/bindings/clock/ |
| D | microchip,xec-pcr.yaml | 17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
22 PWM and TACH clock domain divided down from 48 MHz AHB clock. The
43 32KHz clock monitor minimum valid 32KHz period in 48MHz units
49 32KHz clock monitor maximum valid 32KHz period in 48MHz units
75 default: 30
|
| /Zephyr-latest/soc/arm/beetle/ |
| D | soc_pll.h | 23 * - PLL_FEEDDIV [30:24]
27 * The Fin = 24Mhz on Beetle
35 * PLL_FEEDDIV = 2*(R[30:24] + 1)
|
| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_ast10x0.c | 18 #define HPLL_FREQ MHZ(1000)
38 #define I3C_CLK_DIV_SEL GENMASK(30, 28)
43 #define HCLK_DIV_SEL GENMASK(30, 28)
110 src = MHZ(480); in aspeed_clock_control_get_rate()
140 *rate = MHZ(24) / 13; in aspeed_clock_control_get_rate()
|
| /Zephyr-latest/boards/shields/weact_ov2640_cam_module/boards/ |
| D | mini_stm32h743.overlay | 8 * The OV2640 PCLK is around 72 MHz for QQVGA resolution (160x120) with MCO1_SEL_HSI48
41 ov2640: ov2640@30 {
|
| /Zephyr-latest/soc/ti/lm3s6965/ |
| D | soc.h | 23 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(12)
55 #define IRQ_GPIO_PORTF 30
|
| /Zephyr-latest/soc/intel/apollo_lake/doc/ |
| D | supported_features.txt | 25 | [31] | [30:16] | [15:1] | [0] |
32 Typically, the master clock is 100MHz, and the firmware by default sets
34 results in the de-facto standard 1.8432MHz master clock and a max baud rate
|
| /Zephyr-latest/tests/drivers/clock_control/nrf_clock_control/src/ |
| D | main.c | 21 .frequency = MHZ(128),
26 .frequency = MHZ(320),
31 .frequency = MHZ(64),
40 .frequency = MHZ(16),
45 .frequency = MHZ(16),
50 .frequency = MHZ(16),
51 .accuracy = 30,
66 .frequency = MHZ(16),
71 .frequency = MHZ(19),
76 .frequency = MHZ(16),
[all …]
|
| /Zephyr-latest/boards/pjrc/teensy4/ |
| D | teensy4-pinctrl.dtsi | 20 nxp,speed = "100-mhz";
35 nxp,speed = "200-mhz";
49 nxp,speed = "200-mhz";
60 nxp,speed = "100-mhz";
72 nxp,speed = "100-mhz";
77 /* FLEXCAN3 TX, RX on Teensy-Pins 31/30 */
84 nxp,speed = "100-mhz";
97 nxp,speed = "100-mhz";
110 nxp,speed = "100-mhz";
123 nxp,speed = "100-mhz";
[all …]
|
| /Zephyr-latest/boards/gaisler/generic_leon3/doc/ |
| D | index.rst | 45 Detected frequency: 50.0 MHz
77 *** Booting Zephyr OS build zephyr-v2.4.0-30-ga124c31ec4cf ***
97 system frequency: 50.000 MHz
114 *** Booting Zephyr OS build zephyr-v2.4.0-30-ga124c31ec4cf ***
|
| /Zephyr-latest/drivers/wifi/nrf_wifi/ |
| D | Kconfig.nrfwifi | 236 int "PCB loss for 5 GHz band (5150 MHz - 5350 MHz, Channel-32 - Channel-68)"
245 int "PCB loss for 5 GHz band (5470 MHz - 5730 MHz, Channel-96 - Channel-144)"
254 int "PCB loss for 5 GHz band (5730 MHz - 5895 MHz, Channel-149 - Channel-177)"
268 int "Antenna gain for 5 GHz band (5150 MHz - 5350 MHz)"
273 int "Antenna gain for 5 GHz band (5470 MHz - 5730 MHz)"
278 int "Antenna gain for 5 GHz band (5730 MHz - 5895 MHz)"
588 default 30
640 range 1 30
772 range 30 3600
|
| /Zephyr-latest/soc/espressif/common/ |
| D | Kconfig.spiram | 87 bool "20MHz clock speed"
91 bool "26MHz clock speed"
95 bool "40MHz clock speed"
98 bool "80MHz clock speed"
102 bool "120MHz clock speed"
116 default 30
|
| /Zephyr-latest/drivers/audio/ |
| D | tlv320dac310x.h | 33 #define DAC_PROC_CLK_FREQ_MAX 49152000 /* 49.152 MHz */
41 #define DAC_MOD_CLK_FREQ_MIN 2800000 /* 2.8 MHz */
42 #define DAC_MOD_CLK_FREQ_MAX 6200000 /* 6.2 MHz */
60 #define BCLK_DIV_ADDR (struct reg_addr){0, 30}
|
| /Zephyr-latest/drivers/sdhc/ |
| D | sdhc_esp32.h | 10 #define SDMMC_FREQ_52M 52000 /*!< MMC 52MHz speed */
11 #define SDMMC_FREQ_26M 26000 /*!< MMC 26MHz speed */
57 #define SD_OCR_SDHC_CAP (1 << 30)
|
| /Zephyr-latest/boards/nxp/frdm_mcxn236/ |
| D | board.c | 23 /* Core clock frequency: 150MHz */
77 /* Enable FRO HF(48MHz) output */ in frdm_mcxn236_init()
103 /* Set up PLL1 for 80 MHz FlexCAN clock */ in frdm_mcxn236_init()
244 /* xtal = 20 ~ 30MHz */ in frdm_mcxn236_init()
277 * 0 <- 12MHz FRO in frdm_mcxn236_init()
289 /* Value here should not exceed 25MHZ when using lptmr */ in frdm_mcxn236_init()
290 CLOCK_SetupExtClocking(MHZ(24)); in frdm_mcxn236_init()
|
| /Zephyr-latest/dts/arm/atmel/ |
| D | samd5x.dtsi | 107 interrupts = <29 0>, <30 0>;
321 * 16 MHz max, source clock must not exceed 100 MHz.
324 * -> 48 MHz GCLK(2) / 4 = 12 MHz
343 * 16 MHz max, source clock must not exceed 100 MHz.
346 * -> 48 MHz GCLK(2) / 4 = 12 MHz
375 clocks = <&gclk 30>, <&mclk 0x1c 5>;
|
| /Zephyr-latest/boards/st/nucleo_u031r8/doc/ |
| D | index.rst | 36 They operate at a frequency of up to 56 MHz.
45 - 30 nA Standby mode (6 wake-up pins) without RTC
50 - 52 µA/MHz Run mode
55 - 32-bit Arm |reg| Cortex |reg|-M0+ CPU, frequency up to 56 MHz
63 - 1.13 DMIPS/MHz (Drystone 2.1)
64 - 134 CoreMark |reg| (2.4 CoreMark/MHz at 56 MHz)
80 - 4 to 48 MHz crystal oscillator
82 - Internal 16 MHz factory-trimmed RC (±1%)
84 - Internal multispeed 100 kHz to 48 MHz oscillator,
182 48MHz, driven by 4MHz medium speed internal oscillator.
|
| /Zephyr-latest/boards/nxp/frdm_mcxn947/ |
| D | board.c | 27 /* Core clock frequency: 150MHz */
102 /* Enable FRO HF(48MHz) output */ in frdm_mcxn947_init()
135 /* Set up PLL1 for 80 MHz FlexCAN clock */ in frdm_mcxn947_init()
272 /* Drive CLKOUT from main clock, divided by 25 to yield 6MHz clock in frdm_mcxn947_init()
312 /* xtal = 20 ~ 30MHz */ in frdm_mcxn947_init()
342 * 0 <- 12MHz FRO in frdm_mcxn947_init()
354 /* Value here should not exceed 25MHZ when using lptmr */ in frdm_mcxn947_init()
355 CLOCK_SetupExtClocking(MHZ(24)); in frdm_mcxn947_init()
367 /* Enable 1MHz clock. */ in frdm_mcxn947_init()
374 /* Attach PLL0 clock to I3C, 150MHz / 6 = 25MHz. */ in frdm_mcxn947_init()
|
