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/Zephyr-latest/soc/snps/arc_iot/
Dsysconf.c11 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(16)
30 /* the following configuration is based on Fin = 16 Mhz */
32 {100, PLL_CONF_VAL(1, 25, 2)}, /* 100 Mhz */
33 {50, PLL_CONF_VAL(1, 25, 3)}, /* 50 Mhz */
34 {150, PLL_CONF_VAL(4, 75, 1)}, /* 150 Mhz */
35 {75, PLL_CONF_VAL(4, 75, 2)}, /* 75 Mhz */
36 {25, PLL_CONF_VAL(2, 25, 3)}, /* 25 Mhz */
37 {72, PLL_CONF_VAL(8, 144, 2)}, /* 72 Mhz */
38 {144, PLL_CONF_VAL(8, 144, 1)}, /* 144 Mhz */
51 * 1 Mhz <= Fref <= 50 Mhz
[all …]
/Zephyr-latest/dts/bindings/mmc/
Dst,stm32-sdmmc.yaml46 Clock division factor for SDMMC. Typically the clock operates at 25MHz so
47 a division factor of 2 would be 25MHz / 2 = 12.5MHz.
/Zephyr-latest/soc/nxp/imx/imx8m/m4_quad/
Dsoc.c52 * Switch AHB NOC root to 25M first in order to configure in SOC_ClockInit()
57 /* Switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ in SOC_ClockInit()
61 * Switch AXI M4 root to 25M first in order to configure in SOC_ClockInit()
71 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
73 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
77 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
79 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
83 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
85 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
89 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
[all …]
/Zephyr-latest/soc/gd/gd32/common/
Dpinctrl_soc.h34 * - 13-25: Reserved.
39 * - 20-25: Reserved.
107 /** Maximum 2MHz */
112 /** Maximum 10MHz */
114 /** Maximum 50MHz */
117 /** Maximum 25MHz */
119 /** Maximum 50MHz */
126 /** Maximum 10MHz */
128 /** Maximum 2MHz */
130 /** Maximum 50MHz */
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/
Dhse25.overlay19 clock-frequency = <DT_FREQ_M(25)>;
20 hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
26 clock-frequency = <DT_FREQ_M(25)>;
Dpll_hse25_100.overlay19 hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
20 clock-frequency = <DT_FREQ_M(25)>;
Dpll_hse25_240.overlay19 hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
21 clock-frequency = <DT_FREQ_M(25)>;
Dpll_hse25_ahb_2_100.overlay14 hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
15 clock-frequency = <DT_FREQ_M(25)>;
/Zephyr-latest/drivers/modem/
DKconfig.hl780079 bool "Band 1 (2000MHz)"
82 Enable Band 1 (2000MHz)
85 bool "Band 2 (1900MHz)"
88 Enable Band 2 (1900MHz)
91 bool "Band 3 (1800MHz)"
94 Enable Band 3 (1800MHz)
97 bool "Band 4 (1700MHz)"
100 Enable Band 4 (1700MHz)
103 bool "Band 5 (850MHz)"
106 Enable Band 5 (850MHz)
[all …]
/Zephyr-latest/boards/nxp/ls1046ardb/
Dls1046ardb_ls1046a_defconfig7 # 25 MHz system clock
Dls1046ardb_ls1046a_smp_4cores_defconfig6 # 25 MHz system clock
Dls1046ardb_ls1046a_smp_defconfig6 # 25 MHz system clock
/Zephyr-latest/soc/nuvoton/npcx/
DKconfig51 bool "SPI flash max clock rate of 20 MHz"
54 bool "SPI flash max clock rate of 25 MHz"
57 bool "SPI flash max clock rate of 33 MHz"
61 bool "SPI flash max clock rate of 40 MHz"
64 bool "SPI flash max clock rate of 50 MHz"
70 default 25 if NPCX_HEADER_SPI_MAX_CLOCK_25
/Zephyr-latest/boards/shields/st_b_lcd40_dsi1_mb1166/boards/
Dstm32h747i_disco_stm32h747xx_m7.overlay28 div-r = <24>; /* 27.5 MHz */
37 * = 25 MHz / 5 * 2 * 100 / 2 / (1<<0) / 8 = 62.5 MHz
/Zephyr-latest/tests/drivers/pinctrl/gd32/boards/
Dgd32f450i_eval.overlay45 slew-rate = "max-speed-2mhz";
49 slew-rate = "max-speed-25mhz";
53 slew-rate = "max-speed-50mhz";
57 slew-rate = "max-speed-200mhz";
/Zephyr-latest/dts/bindings/ethernet/
Dmicrochip,ksz8081.yaml24 - "rmii-25MHz"
Dti,dp83825.yaml23 - "rmii-25MHz"
/Zephyr-latest/soc/microchip/mec/
DKconfig37 bool "SPI flash clock rate of 12 MHz"
40 bool "SPI flash clock rate of 16 MHz"
43 bool "SPI flash clock rate of 24 MHz"
46 bool "SPI flash clock rate of 48 MHz"
53 default 25 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_16
65 bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
268 and main 96 MHz clock (MCK):
/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dboard.c27 /* Core clock frequency: 150MHz */
102 /* Enable FRO HF(48MHz) output */ in frdm_mcxn947_init()
135 /* Set up PLL1 for 80 MHz FlexCAN clock */ in frdm_mcxn947_init()
272 /* Drive CLKOUT from main clock, divided by 25 to yield 6MHz clock in frdm_mcxn947_init()
277 CLOCK_SetClkDiv(kCLOCK_DivClkOut, 25U); in frdm_mcxn947_init()
312 /* xtal = 20 ~ 30MHz */ in frdm_mcxn947_init()
342 * 0 <- 12MHz FRO in frdm_mcxn947_init()
354 /* Value here should not exceed 25MHZ when using lptmr */ in frdm_mcxn947_init()
355 CLOCK_SetupExtClocking(MHZ(24)); in frdm_mcxn947_init()
367 /* Enable 1MHz clock. */ in frdm_mcxn947_init()
[all …]
/Zephyr-latest/modules/hal_gigadevice/
DKconfig43 bool "8MHz"
46 Use 8MHz oscillator for HXTAL
49 bool "25MHz"
52 Use 25MHz oscillator for HXTAL
/Zephyr-latest/boards/makerbase/mks_canable_v20/
Dmks_canable_v20.dts39 /* Internal 16 MHz clock used to drive PLL */
44 /* Internal 48 MHz clock used to drive USB */
48 /* Adjust the pll for a SYSTEM Clock of 160 MHz */
84 clocks = <&rcc STM32_CLOCK(APB1, 25U)>,
/Zephyr-latest/boards/pjrc/teensy4/
Dteensy4-pinctrl.dtsi20 nxp,speed = "100-mhz";
35 nxp,speed = "200-mhz";
49 nxp,speed = "200-mhz";
60 nxp,speed = "100-mhz";
72 nxp,speed = "100-mhz";
84 nxp,speed = "100-mhz";
97 nxp,speed = "100-mhz";
110 nxp,speed = "100-mhz";
115 /* LPI2C4 SCL, SDA on Teensy-Pins 24/25 */
123 nxp,speed = "100-mhz";
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dgd,gd32-pinctrl-af.yaml73 signal (default: 2MHz).
101 default: "max-speed-2mhz"
103 - "max-speed-2mhz"
104 - "max-speed-25mhz"
105 - "max-speed-50mhz"
106 - "max-speed-200mhz"
109 slew rate of the output signal. Defaults to "max-speed-2mhz", the SoC
/Zephyr-latest/samples/boards/st/mco/boards/
Dnucleo_f446ze.overlay1 /* Enable the PLLI2s and set it as clock source for the MCO2 (with prescaler 2) : 25MHz */
/Zephyr-latest/soc/microchip/mec/mec15xx/
Dpower.c19 * Lower power dissipation, 48MHz PLL is off
22 * between 16 to 25 MHz. Minimum 3ms until PLL reaches lock
23 * frequency of 48MHz.
34 * possibly polling the DUT then MEC1501 will not shut off its 48MHz
85 * Higher power dissipation, 48MHz PLL remains on.

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