Lines Matching +full:25 +full:mhz
27 /* Core clock frequency: 150MHz */
102 /* Enable FRO HF(48MHz) output */ in frdm_mcxn947_init()
135 /* Set up PLL1 for 80 MHz FlexCAN clock */ in frdm_mcxn947_init()
272 /* Drive CLKOUT from main clock, divided by 25 to yield 6MHz clock in frdm_mcxn947_init()
277 CLOCK_SetClkDiv(kCLOCK_DivClkOut, 25U); in frdm_mcxn947_init()
312 /* xtal = 20 ~ 30MHz */ in frdm_mcxn947_init()
342 * 0 <- 12MHz FRO in frdm_mcxn947_init()
354 /* Value here should not exceed 25MHZ when using lptmr */ in frdm_mcxn947_init()
355 CLOCK_SetupExtClocking(MHZ(24)); in frdm_mcxn947_init()
367 /* Enable 1MHz clock. */ in frdm_mcxn947_init()
374 /* Attach PLL0 clock to I3C, 150MHz / 6 = 25MHz. */ in frdm_mcxn947_init()