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/Zephyr-Core-3.5.0/boards/arm/reel_board/
Dreel_board_v2-pinctrl.dtsi11 <NRF_PSEL(SPIM_MISO, 0, 21)>;
19 <NRF_PSEL(SPIM_MISO, 0, 21)>;
Dreel_board-pinctrl.dtsi11 <NRF_PSEL(SPIM_MISO, 0, 21)>;
19 <NRF_PSEL(SPIM_MISO, 0, 21)>;
/Zephyr-Core-3.5.0/samples/userspace/shared_mem/src/
Dmain.h54 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25}
56 17, 18, 19, 20, 21, 22, 23, 24, 25, 5, 0, 4, 1, 3, 2}
58 15, 14, 17, 16, 19, 18, 21, 20, 23, 22, 25, 24}
/Zephyr-Core-3.5.0/boards/arm/nrf9160dk_nrf9160/dts/
Dnrf9160dk_uart1_on_if0_3.dtsi12 <NRF_PSEL(UART_RTS, 0, 21)>,
21 <NRF_PSEL(UART_RTS, 0, 21)>,
/Zephyr-Core-3.5.0/dts/bindings/sensor/
Dst,stm32-temp.yaml18 STM32F4 Table 6.3.21 default 2.5
27 STM32F4 Table 6.3.21 default 760
/Zephyr-Core-3.5.0/boards/arm/ubx_bmd380eval_nrf52840/
Dubx_bmd380eval_nrf52840-pinctrl.dtsi93 <NRF_PSEL(SPIM_MISO, 0, 21)>;
101 <NRF_PSEL(SPIM_MISO, 0, 21)>;
110 <NRF_PSEL(QSPI_IO1, 0, 21)>,
121 <NRF_PSEL(QSPI_IO1, 0, 21)>,
/Zephyr-Core-3.5.0/boards/arm/xiao_ble/
Dxiao_ble-pinctrl.dtsi88 psels = <NRF_PSEL(SPIM_SCK, 0, 21)>,
96 psels = <NRF_PSEL(SPIM_SCK, 0, 21)>,
105 psels = <NRF_PSEL(QSPI_SCK, 0, 21)>,
116 psels = <NRF_PSEL(QSPI_SCK, 0, 21)>,
/Zephyr-Core-3.5.0/soc/x86/apollo_lake/
Dsoc_gpio.h44 #define APL_GPIO_21 21
78 #define APL_GPIO_65 21
128 #define APL_GPIO_PMC_SPI_RXD 21
162 #define APL_GPIO_97 21
211 #define APL_GPIO_151 21
262 #define APL_GPIO_179 21
/Zephyr-Core-3.5.0/soc/riscv/riscv-ite/it8xxx2/
Dilm.c198 SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21),
199 SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21),
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/clock/
Dgd32a50x-clocks.h40 #define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(AHBEN, 21U)
51 #define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U)
67 #define GD32_CLOCK_TIMER20 GD32_CLOCK_CONFIG(APB2EN, 21U)
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/reset/
Dgd32a50x.h41 #define GD32_RESET_GPIOE GD32_RESET_CONFIG(AHBRST, 21U)
52 #define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U)
68 #define GD32_RESET_TIMER20 GD32_RESET_CONFIG(APB2RST, 21U)
/Zephyr-Core-3.5.0/dts/bindings/gpio/
Darduino-nano-header-r3.yaml16 through 13 correspond to D0 through D13, and parent pins 14 through 21
23 2 D2 A7/D21 21
Dparticle-gen3-header.yaml18 from the bottom; and pins 9 through 21 correspond to pins on the
23 21 RESETn
Dti,boosterpack-header.yaml14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
17 1 3.3V 21 5V 40 GPIO 20 GND
Darduino-header-r3.yaml24 through 5 correspond to A0 through A5, and parent pins 6 through 21
27 D15 21
Darduino-mkr-header.yaml18 through 14 correspond to D0 through D21, and parent pins 15 through 21
28 21 A6/D21 D12/SCL 12
/Zephyr-Core-3.5.0/dts/arm/microchip/
Dmec172xnsz.dtsi83 direct-capable-girqs = <13 14 15 16 17 18 19 20 21 23>;
97 16 17 18 21 22 24 25
108 16 17 18 19 20 21 22 23
119 16 17 18 19 20 21 22 23
130 16 17 18 19 20 21 22 23
141 16 17 18 19 20 21 22 23
186 16 17 20 21 22 23>;
195 10 20 21 22 23
247 20 21 22 23 24 25 26 27>;
339 girqs = <21 2>;
[all …]
/Zephyr-Core-3.5.0/boards/arm/particle_argon/dts/
Dmesh_feather-pinctrl.dtsi26 <NRF_PSEL(SPIM_MISO, 0, 21)>;
34 <NRF_PSEL(SPIM_MISO, 0, 21)>;
/Zephyr-Core-3.5.0/boards/arm/particle_boron/dts/
Dmesh_feather-pinctrl.dtsi26 <NRF_PSEL(SPIM_MISO, 0, 21)>;
34 <NRF_PSEL(SPIM_MISO, 0, 21)>;
/Zephyr-Core-3.5.0/boards/arm/particle_xenon/dts/
Dmesh_feather-pinctrl.dtsi26 <NRF_PSEL(SPIM_MISO, 0, 21)>;
34 <NRF_PSEL(SPIM_MISO, 0, 21)>;
/Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/common/
Dpinctrl_soc.h89 #define MIO_PIN_SPECIAL_MASK_SDIO0_CD GENMASK(21, 16)
99 #define MIO_PIN_SPECIAL_MASK_SDIO1_CD GENMASK(21, 16)
129 #define MIO21 21
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
172 #define MIO_GROUP_SPI0_0_GRP_PINS 16, 17, 21
200 #define MIO_GROUP_SDIO0_0_GRP_PINS 16, 17, 18, 19, 20, 21
212 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
217 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23
232 #define MIO_GROUP_CAN1_3_GRP_PINS 20, 21
255 #define MIO_GROUP_UART1_3_GRP_PINS 20, 21
[all …]
/Zephyr-Core-3.5.0/boards/arm/ubx_bmd345eval_nrf52840/
Dubx_bmd345eval_nrf52840-pinctrl.dtsi108 <NRF_PSEL(SPIM_MISO, 0, 21)>;
116 <NRF_PSEL(SPIM_MISO, 0, 21)>;
142 <NRF_PSEL(QSPI_IO1, 0, 21)>,
153 <NRF_PSEL(QSPI_IO1, 0, 21)>,
/Zephyr-Core-3.5.0/boards/arm/degu_evk/
Ddegu_evk-pinctrl.dtsi12 <NRF_PSEL(UART_CTS, 0, 21)>;
21 <NRF_PSEL(UART_CTS, 0, 21)>;
/Zephyr-Core-3.5.0/boards/arm/raytac_mdbt50q_db_40_nrf52840/
Draytac_mdbt50q_db_40_nrf52840-pinctrl.dtsi133 <NRF_PSEL(SPIM_MISO, 0, 21)>;
141 <NRF_PSEL(SPIM_MISO, 0, 21)>;
150 <NRF_PSEL(QSPI_IO1, 0, 21)>,
161 <NRF_PSEL(QSPI_IO1, 0, 21)>,
/Zephyr-Core-3.5.0/boards/arm/ubx_bmd340eval_nrf52840/
Dubx_bmd340eval_nrf52840-pinctrl.dtsi123 <NRF_PSEL(SPIM_MISO, 0, 21)>;
131 <NRF_PSEL(SPIM_MISO, 0, 21)>;
140 <NRF_PSEL(QSPI_IO1, 0, 21)>,
151 <NRF_PSEL(QSPI_IO1, 0, 21)>,

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