1/*
2 * Copyright (c) 2022 Nordic Semiconductor
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	uart0_default: uart0_default {
8		group1 {
9			psels = <NRF_PSEL(UART_TX, 0, 6)>,
10				<NRF_PSEL(UART_RX, 0, 8)>,
11				<NRF_PSEL(UART_RTS, 0, 5)>,
12				<NRF_PSEL(UART_CTS, 0, 7)>;
13		};
14	};
15
16	uart0_sleep: uart0_sleep {
17		group1 {
18			psels = <NRF_PSEL(UART_TX, 0, 6)>,
19				<NRF_PSEL(UART_RX, 0, 8)>,
20				<NRF_PSEL(UART_RTS, 0, 5)>,
21				<NRF_PSEL(UART_CTS, 0, 7)>;
22			low-power-enable;
23		};
24	};
25
26	i2c0_default: i2c0_default {
27		group1 {
28			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
29				<NRF_PSEL(TWIM_SCL, 0, 27)>;
30		};
31	};
32
33	i2c0_sleep: i2c0_sleep {
34		group1 {
35			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
36				<NRF_PSEL(TWIM_SCL, 0, 27)>;
37			low-power-enable;
38		};
39	};
40
41	i2c1_default: i2c1_default {
42		group1 {
43			psels = <NRF_PSEL(TWIM_SDA, 0, 30)>,
44				<NRF_PSEL(TWIM_SCL, 0, 31)>;
45		};
46	};
47
48	i2c1_sleep: i2c1_sleep {
49		group1 {
50			psels = <NRF_PSEL(TWIM_SDA, 0, 30)>,
51				<NRF_PSEL(TWIM_SCL, 0, 31)>;
52			low-power-enable;
53		};
54	};
55
56	pwm0_default: pwm0_default {
57		group1 {
58			psels = <NRF_PSEL(PWM_OUT0, 0, 13)>;
59			nordic,invert;
60		};
61	};
62
63	pwm0_sleep: pwm0_sleep {
64		group1 {
65			psels = <NRF_PSEL(PWM_OUT0, 0, 13)>;
66			low-power-enable;
67		};
68	};
69
70	spi0_default: spi0_default {
71		group1 {
72			psels = <NRF_PSEL(SPIM_SCK, 0, 27)>,
73				<NRF_PSEL(SPIM_MOSI, 0, 26)>,
74				<NRF_PSEL(SPIM_MISO, 0, 29)>;
75		};
76	};
77
78	spi0_sleep: spi0_sleep {
79		group1 {
80			psels = <NRF_PSEL(SPIM_SCK, 0, 27)>,
81				<NRF_PSEL(SPIM_MOSI, 0, 26)>,
82				<NRF_PSEL(SPIM_MISO, 0, 29)>;
83			low-power-enable;
84		};
85	};
86
87	spi1_default: spi1_default {
88		group1 {
89			psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
90				<NRF_PSEL(SPIM_MOSI, 0, 30)>,
91				<NRF_PSEL(SPIM_MISO, 1, 8)>;
92		};
93	};
94
95	spi1_sleep: spi1_sleep {
96		group1 {
97			psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
98				<NRF_PSEL(SPIM_MOSI, 0, 30)>,
99				<NRF_PSEL(SPIM_MISO, 1, 8)>;
100			low-power-enable;
101		};
102	};
103
104	spi2_default: spi2_default {
105		group1 {
106			psels = <NRF_PSEL(SPIM_SCK, 0, 19)>,
107				<NRF_PSEL(SPIM_MOSI, 0, 20)>,
108				<NRF_PSEL(SPIM_MISO, 0, 21)>;
109		};
110	};
111
112	spi2_sleep: spi2_sleep {
113		group1 {
114			psels = <NRF_PSEL(SPIM_SCK, 0, 19)>,
115				<NRF_PSEL(SPIM_MOSI, 0, 20)>,
116				<NRF_PSEL(SPIM_MISO, 0, 21)>;
117			low-power-enable;
118		};
119	};
120
121	spi3_default: spi3_default {
122		group1 {
123			psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
124				<NRF_PSEL(SPIM_MISO, 1, 14)>,
125				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
126		};
127	};
128
129	spi3_sleep: spi3_sleep {
130		group1 {
131			psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
132				<NRF_PSEL(SPIM_MISO, 1, 14)>,
133				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
134			low-power-enable;
135		};
136	};
137
138	qspi_default: qspi_default {
139		group1 {
140			psels = <NRF_PSEL(QSPI_SCK, 0, 19)>,
141				<NRF_PSEL(QSPI_IO0, 0, 20)>,
142				<NRF_PSEL(QSPI_IO1, 0, 21)>,
143				<NRF_PSEL(QSPI_IO2, 0, 22)>,
144				<NRF_PSEL(QSPI_IO3, 0, 23)>,
145				<NRF_PSEL(QSPI_CSN, 0, 17)>;
146		};
147	};
148
149	qspi_sleep: qspi_sleep {
150		group1 {
151			psels = <NRF_PSEL(QSPI_SCK, 0, 19)>,
152				<NRF_PSEL(QSPI_IO0, 0, 20)>,
153				<NRF_PSEL(QSPI_IO1, 0, 21)>,
154				<NRF_PSEL(QSPI_IO2, 0, 22)>,
155				<NRF_PSEL(QSPI_IO3, 0, 23)>,
156				<NRF_PSEL(QSPI_CSN, 0, 17)>;
157			low-power-enable;
158		};
159	};
160
161};
162