1/* 2 * Copyright (c) 2021 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8 9#include <zephyr/dt-bindings/adc/adc.h> 10#include <zephyr/dt-bindings/clock/mchp_xec_pcr.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h> 13#include <zephyr/dt-bindings/i2c/i2c.h> 14#include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h> 15#include <freq.h> 16#include <mem.h> 17 18#include "mec172x/mec172x-vw-routing.dtsi" 19 20/ { 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-m4"; 28 reg = <0>; 29 cpu-power-states = <&idle &suspend_to_ram>; 30 }; 31 32 power-states { 33 idle: idle { 34 compatible = "zephyr,power-state"; 35 power-state-name = "suspend-to-idle"; 36 min-residency-us = <1000000>; 37 }; 38 39 suspend_to_ram: suspend_to_ram { 40 compatible = "zephyr,power-state"; 41 power-state-name = "suspend-to-ram"; 42 min-residency-us = <2000000>; 43 }; 44 }; 45 }; 46 47 flash0: flash@c0000 { 48 reg = <0x000C0000 0x58000>; 49 }; 50 51 sram0: memory@118000 { 52 compatible = "mmio-sram"; 53 reg = <0x00118000 0x10000>; 54 }; 55 56 soc { 57 ecs: ecs@4000fc00 { 58 reg = <0x4000fc00 0x200>; 59 }; 60 pcr: pcr@40080100 { 61 compatible = "microchip,xec-pcr"; 62 reg = <0x40080100 0x100 0x4000a400 0x100>; 63 reg-names = "pcrr", "vbatr"; 64 interrupts = <174 0>; 65 core-clock-div = <1>; 66 /* MEC172x allows sources to be different */ 67 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>; 68 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>; 69 clk32kmon-period-min = <1435>; 70 clk32kmon-period-max = <1495>; 71 clk32kmon-duty-cycle-var-max = <132>; 72 clk32kmon-valid-min = <4>; 73 xtal-enable-delay-ms = <300>; 74 pll-lock-timeout-ms = <30>; 75 /* pin configured only if one of the sources is set to PIN */ 76 pinctrl-0 = <&clk_32khz_in_gpio165>; 77 pinctrl-names = "default"; 78 #clock-cells = <3>; 79 }; 80 ecia: ecia@4000e000 { 81 compatible = "microchip,xec-ecia"; 82 reg = <0x4000e000 0x400>; 83 direct-capable-girqs = <13 14 15 16 17 18 19 20 21 23>; 84 clocks = <&pcr 1 0 MCHP_XEC_PCR_CLK_PERIPH>; 85 #address-cells = <1>; 86 #size-cells = <1>; 87 88 ranges = <0x0 0x4000e000 0x400>; 89 90 girq8: girq8@0 { 91 compatible = "microchip,xec-ecia-girq"; 92 reg = <0x0 0x14>; 93 interrupts = <0 0>; 94 girq-id = <0>; 95 sources = <0 1 2 3 4 5 6 7 96 8 9 10 11 12 13 14 15 97 16 17 18 21 22 24 25 98 26 27 28 29>; 99 status = "disabled"; 100 }; 101 girq9: girq9@14 { 102 compatible = "microchip,xec-ecia-girq"; 103 reg = <0x14 0x14>; 104 interrupts = <1 0>; 105 girq-id = <1>; 106 sources = <0 1 2 3 4 5 6 7 107 8 9 10 11 12 13 14 15 108 16 17 18 19 20 21 22 23 109 24 25 26 27 28 29>; 110 status = "disabled"; 111 }; 112 girq10: girq10@28 { 113 compatible = "microchip,xec-ecia-girq"; 114 reg = <0x28 0x14>; 115 interrupts = <2 0>; 116 girq-id = <2>; 117 sources = <0 1 2 3 4 5 6 7 118 8 9 10 11 12 13 14 15 119 16 17 18 19 20 21 22 23 120 24 25 26 27 28 29 30>; 121 status = "disabled"; 122 }; 123 girq11: girq11@3c { 124 compatible = "microchip,xec-ecia-girq"; 125 reg = <0x3c 0x14>; 126 interrupts = <3 0>; 127 girq-id = <3>; 128 sources = <0 1 2 3 4 5 6 7 129 8 9 10 11 12 13 14 15 130 16 17 18 19 20 21 22 23 131 24 25 26 27 28 29 30>; 132 status = "disabled"; 133 }; 134 girq12: girq12@50 { 135 compatible = "microchip,xec-ecia-girq"; 136 reg = <0x50 0x14>; 137 interrupts = <4 0>; 138 girq-id = <4>; 139 sources = <0 1 2 3 4 5 6 7 140 8 9 10 11 12 13 14 15 141 16 17 18 19 20 21 22 23 142 24 25 26 27 28 29 30>; 143 status = "disabled"; 144 }; 145 girq13: girq13@64 { 146 compatible = "microchip,xec-ecia-girq"; 147 reg = <0x64 0x14>; 148 interrupts = <5 0>; 149 girq-id = <5>; 150 sources = <0 1 2 3 4>; 151 status = "disabled"; 152 }; 153 girq14: girq14@78 { 154 compatible = "microchip,xec-ecia-girq"; 155 reg = <0x78 0x14>; 156 interrupts = <6 0>; 157 girq-id = <6>; 158 sources = <0 1 2 3 4 5 6 7 159 8 9 10 11 12 13 14 15>; 160 status = "disabled"; 161 }; 162 girq15: girq15@8c { 163 compatible = "microchip,xec-ecia-girq"; 164 reg = <0x8c 0x14>; 165 interrupts = <7 0>; 166 girq-id = <7>; 167 sources = <0 1 2 3 4 5 6 7 168 8 9 10 11 12 13 14 15 169 16 17 18 19 20 22>; 170 status = "disabled"; 171 }; 172 girq16: girq16@a0 { 173 compatible = "microchip,xec-ecia-girq"; 174 reg = <0xa0 0x14>; 175 interrupts = <8 0>; 176 girq-id = <8>; 177 sources = <0 2 3>; 178 status = "disabled"; 179 }; 180 girq17: girq17@b4 { 181 compatible = "microchip,xec-ecia-girq"; 182 reg = <0xb4 0x14>; 183 interrupts = <9 0>; 184 girq-id = <9>; 185 sources = <0 1 2 3 4 8 9 10 11 12 13 14 15 186 16 17 20 21 22 23>; 187 status = "disabled"; 188 }; 189 girq18: girq18@c8 { 190 compatible = "microchip,xec-ecia-girq"; 191 reg = <0xc8 0x14>; 192 interrupts = <10 0>; 193 girq-id = <10>; 194 sources = <0 1 2 3 4 5 6 7 195 10 20 21 22 23 196 24 25 26 27 28>; 197 status = "disabled"; 198 }; 199 girq19: girq19@dc { 200 compatible = "microchip,xec-ecia-girq"; 201 reg = <0xdc 0x14>; 202 interrupts = <11 0>; 203 girq-id = <11>; 204 sources = <0 1 2 3 4 5 6 7 8 9 10>; 205 status = "disabled"; 206 }; 207 girq20: girq20@f0 { 208 compatible = "microchip,xec-ecia-girq"; 209 reg = <0xf0 0x14>; 210 interrupts = <12 0>; 211 girq-id = <12>; 212 sources = <3 9>; 213 status = "disabled"; 214 }; 215 girq21: girq21@104 { 216 compatible = "microchip,xec-ecia-girq"; 217 reg = <0x104 0x14>; 218 interrupts = <13 0>; 219 girq-id = <13>; 220 sources = <2 3 4 5 6 7 8 9 10 11 12 13 14 15 221 18 19 25 26>; 222 status = "disabled"; 223 }; 224 girq22: girq22@118 { 225 compatible = "microchip,xec-ecia-girq"; 226 reg = <0x118 0x14>; 227 interrupts = <255 0>; 228 girq-id = <14>; 229 sources = <0 1 2 3 4 5 9 15>; 230 status = "disabled"; 231 }; 232 girq23: girq23@12c { 233 compatible = "microchip,xec-ecia-girq"; 234 reg = <0x12c 0x14>; 235 interrupts = <14 0>; 236 girq-id = <15>; 237 sources = <0 1 2 3 4 5 6 7 8 9 10 16 17>; 238 status = "disabled"; 239 }; 240 girq24: girq24@140 { 241 compatible = "microchip,xec-ecia-girq"; 242 reg = <0x140 0x14>; 243 interrupts = <15 0>; 244 girq-id = <16>; 245 sources = <0 1 2 3 4 5 6 7 8 9 10 11 246 12 13 14 15 16 17 18 19 247 20 21 22 23 24 25 26 27>; 248 status = "disabled"; 249 }; 250 girq25: girq25@154 { 251 compatible = "microchip,xec-ecia-girq"; 252 reg = <0x154 0x14>; 253 interrupts = <16 0>; 254 girq-id = <17>; 255 sources = <0 1 2 3 4 5 6 7 8 9 10 11 256 12 13 14 15>; 257 status = "disabled"; 258 }; 259 girq26: girq26@168 { 260 compatible = "microchip,xec-ecia-girq"; 261 reg = <0x168 0x14>; 262 interrupts = <17 0>; 263 girq-id = <18>; 264 sources = <0 1 2 3 4 5 6 12 13>; 265 status = "disabled"; 266 }; 267 }; 268 pinctrl: pin-controller@40081000 { 269 compatible = "microchip,xec-pinctrl"; 270 #address-cells = <1>; 271 #size-cells = <1>; 272 reg = <0x40081000 0x1000>; 273 274 gpio_000_036: gpio@40081000 { 275 compatible = "microchip,xec-gpio-v2"; 276 reg = < 0x40081000 0x80 0x40081300 0x04 277 0x40081380 0x04 0x400813fc 0x04>; 278 interrupts = <3 2>; 279 gpio-controller; 280 port-id = <0>; 281 girq-id = <11>; 282 #gpio-cells=<2>; 283 }; 284 gpio_040_076: gpio@40081080 { 285 compatible = "microchip,xec-gpio-v2"; 286 reg = < 0x40081080 0x80 0x40081304 0x04 287 0x40081384 0x04 0x400813f8 0x4>; 288 interrupts = <2 2>; 289 gpio-controller; 290 port-id = <1>; 291 girq-id = <10>; 292 #gpio-cells=<2>; 293 }; 294 gpio_100_136: gpio@40081100 { 295 compatible = "microchip,xec-gpio-v2"; 296 reg = < 0x40081100 0x80 0x40081308 0x04 297 0x40081388 0x04 0x400813f4 0x04>; 298 gpio-controller; 299 interrupts = <1 2>; 300 port-id = <2>; 301 girq-id = <9>; 302 #gpio-cells=<2>; 303 }; 304 gpio_140_176: gpio@40081180 { 305 compatible = "microchip,xec-gpio-v2"; 306 reg = < 0x40081180 0x80 0x4008130c 0x04 307 0x4008138c 0x04 0x400813f0 0x04>; 308 gpio-controller; 309 interrupts = <0 2>; 310 port-id = <3>; 311 girq-id = <8>; 312 #gpio-cells=<2>; 313 }; 314 gpio_200_236: gpio@40081200 { 315 compatible = "microchip,xec-gpio-v2"; 316 reg = < 0x40081200 0x80 0x40081310 0x04 317 0x40081390 0x04 0x400813ec 0x04>; 318 gpio-controller; 319 interrupts = <4 2>; 320 port-id = <4>; 321 girq-id = <12>; 322 #gpio-cells=<2>; 323 }; 324 gpio_240_276: gpio@40081280 { 325 compatible = "microchip,xec-gpio-v2"; 326 reg = < 0x40081280 0x80 0x40081314 0x04 327 0x40081394 0x04 0x400813e8 0x04>; 328 gpio-controller; 329 interrupts = <17 2>; 330 port-id = <5>; 331 girq-id = <26>; 332 #gpio-cells=<2>; 333 }; 334 }; 335 wdog: watchdog@40000400 { 336 compatible = "microchip,xec-watchdog"; 337 reg = <0x40000400 0x400>; 338 interrupts = <171 0>; 339 girqs = <21 2>; 340 pcrs = <1 9>; 341 }; 342 rtimer: timer@40007400 { 343 compatible = "microchip,xec-rtos-timer"; 344 reg = <0x40007400 0x10>; 345 interrupts = <111 0>; 346 girqs = <23 10>; 347 }; 348 timer0: timer@40000c00 { 349 compatible = "microchip,xec-timer"; 350 clock-frequency = <48000000>; 351 reg = <0x40000c00 0x20>; 352 interrupts = <136 0>; 353 girqs = <23 0>; 354 pcrs = <1 30>; 355 max-value = <0xFFFF>; 356 prescaler = <0>; 357 status = "disabled"; 358 }; 359 timer1: timer@40000c20 { 360 compatible = "microchip,xec-timer"; 361 clock-frequency = <48000000>; 362 reg = <0x40000c20 0x20>; 363 interrupts = <137 0>; 364 girqs = <23 1>; 365 pcrs = <1 31>; 366 max-value = <0xFFFF>; 367 prescaler = <0>; 368 status = "disabled"; 369 }; 370 timer2: timer@40000c40 { 371 compatible = "microchip,xec-timer"; 372 clock-frequency = <48000000>; 373 reg = <0x40000c40 0x20>; 374 interrupts = <138 0>; 375 girqs = <23 2>; 376 pcrs = <3 21>; 377 max-value = <0xFFFF>; 378 prescaler = <0>; 379 status = "disabled"; 380 }; 381 timer3: timer@40000c60 { 382 compatible = "microchip,xec-timer"; 383 clock-frequency = <48000000>; 384 reg = <0x40000c60 0x20>; 385 interrupts = <139 0>; 386 girqs = <23 3>; 387 pcrs = <3 22>; 388 max-value = <0xFFFF>; 389 prescaler = <0>; 390 status = "disabled"; 391 }; 392 /* 393 * NOTE: When RTOS timer used as kernel timer, timer4 used 394 * to provide high speed busy wait counter. Keep disabled to 395 * prevent counter driver from claiming it. 396 */ 397 timer4: timer@40000c80 { 398 compatible = "microchip,xec-timer"; 399 clock-frequency = <48000000>; 400 reg = <0x40000c80 0x20>; 401 interrupts = <140 0>; 402 girqs = <23 4>; 403 pcrs = <3 23>; 404 max-value = <0xFFFFFFFF>; 405 prescaler = <0>; 406 status = "disabled"; 407 }; 408 timer5: timer@40000ca0 { 409 compatible = "microchip,xec-timer"; 410 clock-frequency = <48000000>; 411 reg = <0x40000ca0 0x20>; 412 interrupts = <141 0>; 413 girqs = <23 5>; 414 pcrs = <3 24>; 415 max-value = <0xFFFFFFFF>; 416 prescaler = <0>; 417 status = "disabled"; 418 }; 419 cntr0: timer@40000d00 { 420 reg = <0x40000d00 0x20>; 421 interrupts = <142 0>; 422 girqs = <23 6>; 423 pcrs = <4 2>; 424 status = "disabled"; 425 }; 426 cntr1: timer@40000d20 { 427 reg = <0x40000d20 0x20>; 428 interrupts = <143 0>; 429 girqs = <23 7>; 430 pcrs = <4 3>; 431 status = "disabled"; 432 }; 433 cntr2: timer@40000d40 { 434 reg = <0x40000d40 0x20>; 435 interrupts = <144 0>; 436 girqs = <23 8>; 437 pcrs = <4 3>; 438 status = "disabled"; 439 }; 440 cntr3: timer@40000d60 { 441 reg = <0x40000d60 0x20>; 442 interrupts = <145 0>; 443 girqs = <23 9>; 444 pcrs = <4 4>; 445 status = "disabled"; 446 }; 447 cctmr0: timer@40001000 { 448 reg = <0x40001000 0x40>; 449 interrupts = <146 0>, <147 0>, <148 0>, <149 0>, 450 <150 0>, <151 0>, <152 0>, <153 0>, 451 <154 0>; 452 girqs = <18 20>, <18 21>, <18 22>, <18 23>, <18 24>, 453 <18 25>, <18 26>, <18 27>, <18 28>; 454 pcrs = <3 30>; 455 status = "disabled"; 456 }; 457 hibtimer0: timer@40009800 { 458 reg = <0x40009800 0x20>; 459 interrupts = <112 0>; 460 girqs = <23 16>; 461 }; 462 hibtimer1: timer@40009820 { 463 reg = <0x40009820 0x20>; 464 interrupts = <113 0>; 465 girqs = <23 17>; 466 }; 467 weektmr0: timer@4000ac80 { 468 reg = <0x4000ac80 0x80>; 469 interrupts = <114 0>, <115 0>, <116 0>, 470 <117 0>, <118 0>; 471 girqs = <21 3>, <21 4>, <21 5>, <21 6>, <21 7>; 472 status = "disabled"; 473 }; 474 bbram: bb-ram@4000a800 { 475 compatible = "microchip,xec-bbram"; 476 reg = <0x4000a800 0x100>; 477 reg-names = "memory"; 478 }; 479 vci0: vci@4000ae00 { 480 reg = <0x4000ae00 0x40>; 481 interrupts = <121 0>, <122 0>, <123 0>, 482 <124 0>, <125 0>; 483 girqs = <21 10>, <21 11>, <21 12>, <21 13>, <21 14>; 484 status = "disabled"; 485 }; 486 dmac: dmac@40002400 { 487 compatible = "microchip,xec-dmac"; 488 reg = <0x40002400 0xc00>; 489 interrupts = <24 1>, <25 1>, <26 1>, <27 1>, 490 <28 1>, <29 1>, <30 1>, <31 1>, 491 <32 1>, <33 1>, <34 1>, <35 1>, 492 <36 1>, <37 1>, <38 1>, <39 1>; 493 girqs = < MCHP_XEC_ECIA(14, 0, 6, 24) 494 MCHP_XEC_ECIA(14, 1, 6, 25) 495 MCHP_XEC_ECIA(14, 2, 6, 26) 496 MCHP_XEC_ECIA(14, 3, 6, 27) 497 MCHP_XEC_ECIA(14, 4, 6, 28) 498 MCHP_XEC_ECIA(14, 5, 6, 29) 499 MCHP_XEC_ECIA(14, 6, 6, 30) 500 MCHP_XEC_ECIA(14, 7, 6, 31) 501 MCHP_XEC_ECIA(14, 8, 6, 32) 502 MCHP_XEC_ECIA(14, 9, 6, 33) 503 MCHP_XEC_ECIA(14, 10, 6, 34) 504 MCHP_XEC_ECIA(14, 11, 6, 35) 505 MCHP_XEC_ECIA(14, 12, 6, 36) 506 MCHP_XEC_ECIA(14, 13, 6, 37) 507 MCHP_XEC_ECIA(14, 14, 6, 38) 508 MCHP_XEC_ECIA(14, 15, 6, 39) >; 509 pcrs = <1 6>; 510 #dma-cells = <2>; 511 dma-channels = <16>; 512 dma-requests = <16>; 513 status = "disabled"; 514 }; 515 eeprom: eeprom@40002c00 { 516 compatible = "microchip,xec-eeprom"; 517 reg = <0x40002c00 0x400>; 518 interrupts = <155 2>; 519 size = <2048>; 520 girqs = <18 13>; 521 pcrs = <4 14>; 522 status = "disabled"; 523 }; 524 i2c_smb_0: i2c@40004000 { 525 compatible = "microchip,xec-i2c-v2"; 526 reg = <0x40004000 0x80>; 527 clock-frequency = <I2C_BITRATE_STANDARD>; 528 interrupts = <20 1>; 529 girqs = <13 0>; 530 pcrs = <1 10>; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 status = "disabled"; 534 }; 535 i2c_smb_1: i2c@40004400 { 536 compatible = "microchip,xec-i2c-v2"; 537 reg = <0x40004400 0x80>; 538 clock-frequency = <I2C_BITRATE_STANDARD>; 539 interrupts = <21 1>; 540 girqs = <13 1>; 541 pcrs = <3 13>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 status = "disabled"; 545 }; 546 i2c_smb_2: i2c@40004800 { 547 compatible = "microchip,xec-i2c-v2"; 548 reg = <0x40004800 0x80>; 549 clock-frequency = <I2C_BITRATE_STANDARD>; 550 interrupts = <22 1>; 551 girqs = <13 2>; 552 pcrs = <3 14>; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 status = "disabled"; 556 }; 557 i2c_smb_3: i2c@40004c00 { 558 compatible = "microchip,xec-i2c-v2"; 559 reg = <0x40004C00 0x80>; 560 clock-frequency = <I2C_BITRATE_STANDARD>; 561 interrupts = <23 1>; 562 girqs = <13 3>; 563 pcrs = <3 15>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 status = "disabled"; 567 }; 568 i2c_smb_4: i2c@40005000 { 569 compatible = "microchip,xec-i2c-v2"; 570 reg = <0x40005000 0x80>; 571 clock-frequency = <I2C_BITRATE_STANDARD>; 572 interrupts = <158 1>; 573 girqs = <13 4>; 574 pcrs = <3 20>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 status = "disabled"; 578 }; 579 ps2_0: ps2@40009000 { 580 compatible = "microchip,xec-ps2"; 581 reg = <0x40009000 0x40>; 582 interrupts = <100 1>; 583 girqs = <18 10>, <21 18>; 584 pcrs = <3 5>; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 status = "disabled"; 588 }; 589 pwm0: pwm@40005800 { 590 compatible = "microchip,xec-pwm"; 591 reg = <0x40005800 0x20>; 592 pcrs = <1 4>; 593 status = "disabled"; 594 #pwm-cells = <3>; 595 }; 596 pwm1: pwm@40005810 { 597 compatible = "microchip,xec-pwm"; 598 reg = <0x40005810 0x20>; 599 pcrs = <1 20>; 600 status = "disabled"; 601 #pwm-cells = <3>; 602 }; 603 pwm2: pwm@40005820 { 604 compatible = "microchip,xec-pwm"; 605 reg = <0x40005820 0x20>; 606 pcrs = <1 21>; 607 status = "disabled"; 608 #pwm-cells = <3>; 609 }; 610 pwm3: pwm@40005830 { 611 compatible = "microchip,xec-pwm"; 612 reg = <0x40005830 0x20>; 613 pcrs = <1 22>; 614 status = "disabled"; 615 #pwm-cells = <3>; 616 }; 617 pwm4: pwm@40005840 { 618 compatible = "microchip,xec-pwm"; 619 reg = <0x40005840 0x20>; 620 pcrs = <1 23>; 621 status = "disabled"; 622 #pwm-cells = <3>; 623 }; 624 pwm5: pwm@40005850 { 625 compatible = "microchip,xec-pwm"; 626 reg = <0x40005850 0x20>; 627 pcrs = <1 24>; 628 status = "disabled"; 629 #pwm-cells = <3>; 630 }; 631 pwm6: pwm@40005860 { 632 compatible = "microchip,xec-pwm"; 633 reg = <0x40005860 0x20>; 634 pcrs = <1 25>; 635 status = "disabled"; 636 #pwm-cells = <3>; 637 }; 638 pwm7: pwm@40005870 { 639 compatible = "microchip,xec-pwm"; 640 reg = <0x40005870 0x20>; 641 pcrs = <1 26>; 642 status = "disabled"; 643 #pwm-cells = <3>; 644 }; 645 pwm8: pwm@40005880 { 646 compatible = "microchip,xec-pwm"; 647 reg = <0x40005880 0x20>; 648 pcrs = <1 27>; 649 status = "disabled"; 650 #pwm-cells = <3>; 651 }; 652 tach0: tach@40006000 { 653 compatible = "microchip,xec-tach"; 654 reg = <0x40006000 0x10>; 655 interrupts = <71 4>; 656 girqs = <17 1>; 657 pcrs = <1 2>; 658 #address-cells = <1>; 659 #size-cells = <0>; 660 status = "disabled"; 661 }; 662 tach1: tach@40006010 { 663 compatible = "microchip,xec-tach"; 664 reg = <0x40006010 0x10>; 665 interrupts = <72 4>; 666 girqs = <17 2>; 667 pcrs = <1 11>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 status = "disabled"; 671 }; 672 tach2: tach@40006020 { 673 compatible = "microchip,xec-tach"; 674 reg = <0x40006020 0x10>; 675 interrupts = <73 4>; 676 girqs = <17 3>; 677 pcrs = <1 12>; 678 #address-cells = <1>; 679 #size-cells = <0>; 680 status = "disabled"; 681 }; 682 tach3: tach@40006030 { 683 compatible = "microchip,xec-tach"; 684 reg = <0x40006030 0x10>; 685 interrupts = <159 4>; 686 girqs = <17 4>; 687 pcrs = <1 13>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 status = "disabled"; 691 }; 692 rpmfan0: rpmfan@4000a000 { 693 reg = <0x4000a000 0x80>; 694 interrupts = <74 1>, <75 1>; 695 girqs = <17 20>, <17 21>; 696 pcrs = <3 12>; 697 status = "disabled"; 698 }; 699 rpmfan1: rpmfan@4000a080 { 700 reg = <0x4000a080 0x80>; 701 interrupts = <76 1>, <77 1>; 702 girqs = <17 22>, <17 23>; 703 pcrs = <4 7>; 704 status = "disabled"; 705 }; 706 adc0: adc@40007c00 { 707 compatible = "microchip,xec-adc"; 708 reg = <0x40007c00 0x90>; 709 interrupts = <78 0>, <79 0>; 710 girqs = <17 8>, <17 9>; 711 pcrs = <3 3>; 712 status = "disabled"; 713 #io-channel-cells = <1>; 714 clktime = <32>; 715 }; 716 kscan0: kscan@40009c00 { 717 compatible = "microchip,xec-kscan"; 718 reg = <0x40009c00 0x18>; 719 interrupts = <135 0>; 720 girqs = <21 25>; 721 pcrs = <3 11>; 722 status = "disabled"; 723 #address-cells = <1>; 724 #size-cells = <0>; 725 }; 726 peci0: peci@40006400 { 727 compatible = "microchip,xec-peci"; 728 reg = <0x40006400 0x80>; 729 interrupts = <70 4>; 730 girqs = <17 0>; 731 pcrs = <1 1>; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 }; 735 spi0: spi@40070000 { 736 reg = <0x40070000 0x400>; 737 interrupts = <91 2>; 738 girqs = < MCHP_XEC_ECIA(18, 1, 10, 91) >; 739 clocks = <&pcr 4 8 MCHP_XEC_PCR_CLK_PERIPH>; 740 clock-frequency = <12000000>; 741 lines = <1>; 742 chip-select = <0>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 status = "disabled"; 746 }; 747 spi1: spi@40009400 { 748 reg = <0x40009400 0x80>; 749 interrupts = <92 2>, <93 2>; 750 girqs = <18 2>, <18 3>; 751 pcrs = <3 9>; 752 status = "disabled"; 753 }; 754 spi2: spi@40009480 { 755 reg = <0x40009480 0x80>; 756 interrupts = <94 2>, <95 2>; 757 girqs = <18 4>, <18 5>; 758 pcrs = <4 22>; 759 status = "disabled"; 760 }; 761 prochot0: prochot@40003400 { 762 reg = <0x40003400 0x20>; 763 interrupts = <87 0>; 764 girqs = <17 17>; 765 pcrs = <4 13>; 766 status = "disabled"; 767 }; 768 rcid0: rcid@40001400 { 769 reg = <0x40001400 0x80>; 770 interrupts = <80 0>; 771 girqs = <17 10>; 772 pcrs = <4 10>; 773 status = "disabled"; 774 }; 775 rcid1: rcid@40001480 { 776 reg = <0x40001480 0x80>; 777 interrupts = <81 0>; 778 girqs = <17 11>; 779 pcrs = <4 11>; 780 status = "disabled"; 781 }; 782 rcid2: rcid@40001500 { 783 reg = <0x40001500 0x80>; 784 interrupts = <82 0>; 785 girqs = <17 12>; 786 pcrs = <4 12>; 787 status = "disabled"; 788 }; 789 spip0: spip@40007000 { 790 reg = <0x40007000 0x100>; 791 interrupts = <90 0>; 792 girqs = <18 0>; 793 pcrs = <4 16>; 794 status = "disabled"; 795 }; 796 bbled0: bbled@4000b800 { 797 reg = <0x4000b800 0x100>; 798 interrupts = <83 0>; 799 girqs = <17 13>; 800 pcrs = <3 16>; 801 status = "disabled"; 802 }; 803 bbled1: bbled@4000b900 { 804 reg = <0x4000b900 0x100>; 805 interrupts = <84 0>; 806 girqs = <17 14>; 807 pcrs = <3 17>; 808 status = "disabled"; 809 }; 810 bbled2: bbled@4000ba00 { 811 reg = <0x4000ba00 0x100>; 812 interrupts = <85 0>; 813 girqs = <17 15>; 814 pcrs = <3 18>; 815 status = "disabled"; 816 }; 817 bbled3: bbled@4000bb00 { 818 reg = <0x4000bb00 0x100>; 819 interrupts = <86 0>; 820 girqs = <17 16>; 821 pcrs = <3 25>; 822 status = "disabled"; 823 }; 824 bclink0: bclink@4000cd00 { 825 reg = <0x4000cd00 0x20>; 826 interrupts = <96 0>, <97 0>; 827 girqs = <18 7>, <18 6>; 828 pcrs = <3 19>; 829 status = "disabled"; 830 }; 831 tfdp0: tfdp@40008c00 { 832 reg = <0x40008c00 0x10>; 833 pcrs = <1 7>; 834 status = "disabled"; 835 }; 836 glblcfg0: glblcfg@400fff00 { 837 reg = <0x400fff00 0x40>; 838 pcrs = <2 12>; 839 status = "disabled"; 840 }; 841 uart0: uart@400f2400 { 842 compatible = "microchip,xec-uart"; 843 reg = <0x400f2400 0x400>; 844 interrupts = <40 1>; 845 clock-frequency = <1843200>; 846 current-speed = <38400>; 847 girqs = <15 0>; 848 pcrs = <2 1>; 849 ldn = <9>; 850 status = "disabled"; 851 }; 852 uart1: uart@400f2800 { 853 compatible = "microchip,xec-uart"; 854 reg = <0x400f2800 0x400>; 855 interrupts = <41 1>; 856 clock-frequency = <1843200>; 857 current-speed = <38400>; 858 girqs = <15 1>; 859 pcrs = <2 2>; 860 ldn = <10>; 861 status = "disabled"; 862 }; 863 espi0: espi@400f3400 { 864 compatible = "microchip,xec-espi-v2"; 865 /* reg tuple contains one 32-bit address cell and one 866 * 32-bit length(size) cell. 867 */ 868 #address-cells = <1>; 869 #size-cells = <1>; 870 reg = < 0x400f3400 0x400 871 0x400f3800 0x400 872 0x400f9c00 0x400>; 873 reg-names = "io", "mem", "vw"; 874 interrupts = <103 3>, <104 3>, <105 3>, <106 3>, 875 <107 3>, <108 3>, <109 3>, <110 2>, 876 <156 3>; 877 interrupt-names = "pc", "bm1", "bm2", "ltr", "oob_up", 878 "oob_dn", "fc", "rst", "vw_chan_en"; 879 girqs = < MCHP_XEC_ECIA(19, 0, 11, 103) 880 MCHP_XEC_ECIA(19, 1, 11, 104) 881 MCHP_XEC_ECIA(19, 2, 11, 105) 882 MCHP_XEC_ECIA(19, 3, 11, 106) 883 MCHP_XEC_ECIA(19, 4, 11, 107) 884 MCHP_XEC_ECIA(19, 5, 11, 108) 885 MCHP_XEC_ECIA(19, 6, 11, 109) 886 MCHP_XEC_ECIA(19, 7, 11, 110) 887 MCHP_XEC_ECIA(19, 8, 11, 156) >; 888 pcrs = <2 19>; 889 status = "disabled"; 890 891 espi_saf0: espi_saf@40008000 { 892 compatible = "microchip,xec-espi-saf-v2"; 893 reg = <0x40008000 0x400>, <0x40070000 0x400>, 894 <0x40071000 0x400>; 895 reg-names = "safbr", "safqspi", "safcomm"; 896 interrupts = <166 3>, <167 3>; 897 interrupt-names = "done", "err"; 898 girqs = < MCHP_XEC_ECIA(19, 9, 11, 166) >, 899 < MCHP_XEC_ECIA(19, 10, 11, 167) >; 900 pcrs = <2 27>; 901 status = "disabled"; 902 }; 903 904 mbox0: mbox@400f0000 { 905 compatible = "microchip,xec-espi-host-dev"; 906 reg = <0x400f0000 0x200>; 907 interrupts = <60 3>; 908 girqs = < MCHP_XEC_ECIA(15, 20, 7, 60) >; 909 pcrs = <2 17>; 910 ldn = <0>; 911 status = "disabled"; 912 }; 913 kbc0: kbc@400f0400 { 914 compatible = "microchip,xec-espi-host-dev"; 915 reg = <0x400f0400 0x400>; 916 interrupts = <58 3>, <59 3>; 917 interrupt-names = "kbc_obe", "kbc_ibf"; 918 girqs = < MCHP_XEC_ECIA(15, 18, 7, 58) 919 MCHP_XEC_ECIA(15, 19, 7, 59) >; 920 ldn = <1>; 921 status = "disabled"; 922 }; 923 acpi_ec0: acpi_ec@400f0800 { 924 compatible = "microchip,xec-espi-host-dev"; 925 reg = <0x400f0800 0x400>; 926 interrupts = <45 3>, <46 3>; 927 interrupt-names = "acpi_ibf", "acpi_obe"; 928 girqs = < MCHP_XEC_ECIA(15, 5, 7, 45) 929 MCHP_XEC_ECIA(15, 6, 7, 46) >; 930 ldn = <2>; 931 status = "disabled"; 932 }; 933 acpi_ec1: acpi_ec@400f0c00 { 934 compatible = "microchip,xec-espi-host-dev"; 935 reg = <0x400f0c00 0x400>; 936 interrupts = <47 3>, <48 3>; 937 interrupt-names = "acpi_ibf", "acpi_obe"; 938 girqs = < MCHP_XEC_ECIA(15, 7, 7, 47) 939 MCHP_XEC_ECIA(15, 8, 7, 48) >; 940 ldn = <3>; 941 status = "disabled"; 942 }; 943 acpi_ec2: acpi_ec@400f1000 { 944 compatible = "microchip,xec-espi-host-dev"; 945 reg = <0x400f1000 0x400>; 946 interrupts = <49 3>, <50 3>; 947 interrupt-names = "acpi_ibf", "acpi_obe"; 948 girqs = < MCHP_XEC_ECIA(15, 9, 7, 49) 949 MCHP_XEC_ECIA(15, 10, 7, 50) >; 950 ldn = <4>; 951 status = "disabled"; 952 }; 953 acpi_ec3: acpi_ec@400f1400 { 954 compatible = "microchip,xec-espi-host-dev"; 955 reg = <0x400f1400 0x400>; 956 interrupts = <51 3>, <52 3>; 957 interrupt-names = "acpi_ibf", "acpi_obe"; 958 girqs = < MCHP_XEC_ECIA(15, 11, 7, 51) 959 MCHP_XEC_ECIA(15, 12, 7, 52) >; 960 ldn = <5>; 961 status = "disabled"; 962 }; 963 acpi_ec4: acpi_ec@400f1800 { 964 compatible = "microchip,xec-espi-host-dev"; 965 reg = <0x400f1800 0x400>; 966 interrupts = <53 3>, <54 3>; 967 interrupt-names = "acpi_ibf", "acpi_obe"; 968 girqs = < MCHP_XEC_ECIA(15, 13, 7, 53) 969 MCHP_XEC_ECIA(15, 14, 7, 54) >; 970 ldn = <6>; 971 status = "disabled"; 972 }; 973 acpi_pm1: acpi_pm1@400f1c00 { 974 compatible = "microchip,xec-espi-host-dev"; 975 reg = <0x400f1c00 0x400>; 976 interrupts = <55 3>, <56 3>, <57 3>; 977 interrupt-names = "pm1_ctl", "pm1_en", "pm1_sts"; 978 girqs = < MCHP_XEC_ECIA(15, 15, 7, 55) 979 MCHP_XEC_ECIA(15, 16, 7, 56) 980 MCHP_XEC_ECIA(15, 17, 7, 57) >; 981 ldn = <7>; 982 status = "disabled"; 983 }; 984 port92: port92@400f2000 { 985 compatible = "microchip,xec-espi-host-dev"; 986 reg = <0x400f2000 0x400>; 987 ldn = <8>; 988 status = "disabled"; 989 }; 990 emi0: emi@400f4000 { 991 compatible = "microchip,xec-espi-host-dev"; 992 reg = <0x400f4000 0x400>; 993 interrupts = <42 3>; 994 girqs = < MCHP_XEC_ECIA(15, 2, 7, 42) >; 995 ldn = <16>; 996 status = "disabled"; 997 }; 998 emi1: emi@400f4400 { 999 compatible = "microchip,xec-espi-host-dev"; 1000 reg = <0x400f4400 0x400>; 1001 interrupts = <43 3>; 1002 girqs = < MCHP_XEC_ECIA(15, 3, 7, 43) >; 1003 ldn = <17>; 1004 status = "disabled"; 1005 }; 1006 emi2: emi@400f4800 { 1007 compatible = "microchip,xec-espi-host-dev"; 1008 reg = <0x400f4800 0x400>; 1009 interrupts = <44 3>; 1010 girqs = < MCHP_XEC_ECIA(15, 4, 7, 44) >; 1011 ldn = <18>; 1012 status = "disabled"; 1013 }; 1014 rtc0: rtc@400f5000 { 1015 compatible = "microchip,xec-espi-host-dev"; 1016 reg = <0x400f5000 0x100>; 1017 interrupts = <119 3>, <120 3>; 1018 girqs = < MCHP_XEC_ECIA(21, 8, 13, 119) 1019 MCHP_XEC_ECIA(21, 9, 13, 120) >; 1020 pcrs = <2 18>; 1021 ldn = <20>; 1022 status = "disabled"; 1023 }; 1024 /* Capture writes to host I/O 0x80 - 0x83 */ 1025 p80bd0: p80bd@400f8000 { 1026 compatible = "microchip,xec-espi-host-dev"; 1027 reg = <0x400f8000 0x400>; 1028 interrupts = <62 0>; 1029 girqs = < MCHP_XEC_ECIA(15, 22, 7, 62) >; 1030 pcrs = <2 25>; 1031 ldn = <32>; 1032 status = "disabled"; 1033 }; 1034 /* Capture writes to an 8-bit I/O and map to one of 0x80 to 0x83 */ 1035 p80bd0_alias: p80bd@400f8400 { 1036 compatible = "microchip,xec-espi-host-dev"; 1037 reg = <0x400f8400 0x400>; 1038 ldn = <33>; 1039 host-io = <0x90>; 1040 /* map 0x90 to 0x80 */ 1041 host-io-addr-mask = <0x01>; 1042 status = "disabled"; 1043 }; 1044 }; 1045 1046 symcr: symcr@40100000 { 1047 compatible = "microchip,xec-symcr"; 1048 reg = <0x40100000 0x1000>; 1049 interrupts = <68 1>; 1050 clocks = <&pcr 3 26 MCHP_XEC_PCR_CLK_PERIPH>; 1051 girqs = <16 3>; 1052 status = "disabled"; 1053 #address-cells = <1>; 1054 #size-cells = <1>; 1055 }; 1056 1057 rom_api: rom_api@1f000 { 1058 reg = <0x1f000 0x1000>; 1059 status = "disabled"; 1060 }; 1061 }; 1062}; 1063 1064&nvic { 1065 arm,num-irq-priority-bits = <3>; 1066}; 1067 1068&systick { 1069 status = "disabled"; 1070}; 1071
