1/*
2 * Copyright (c) 2022 Nordic Semiconductor
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	uart0_default: uart0_default {
8		group1 {
9			psels = <NRF_PSEL(UART_TX, 0, 6)>,
10				<NRF_PSEL(UART_RX, 0, 8)>,
11				<NRF_PSEL(UART_RTS, 0, 5)>,
12				<NRF_PSEL(UART_CTS, 0, 7)>;
13		};
14	};
15
16	uart0_sleep: uart0_sleep {
17		group1 {
18			psels = <NRF_PSEL(UART_TX, 0, 6)>,
19				<NRF_PSEL(UART_RX, 0, 8)>,
20				<NRF_PSEL(UART_RTS, 0, 5)>,
21				<NRF_PSEL(UART_CTS, 0, 7)>;
22			low-power-enable;
23		};
24	};
25
26	uart1_default: uart1_default {
27		group1 {
28			psels = <NRF_PSEL(UART_RX, 1, 1)>,
29				<NRF_PSEL(UART_TX, 1, 2)>;
30		};
31	};
32
33	uart1_sleep: uart1_sleep {
34		group1 {
35			psels = <NRF_PSEL(UART_RX, 1, 1)>,
36				<NRF_PSEL(UART_TX, 1, 2)>;
37			low-power-enable;
38		};
39	};
40
41	i2c0_default: i2c0_default {
42		group1 {
43			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
44				<NRF_PSEL(TWIM_SCL, 0, 27)>;
45		};
46	};
47
48	i2c0_sleep: i2c0_sleep {
49		group1 {
50			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
51				<NRF_PSEL(TWIM_SCL, 0, 27)>;
52			low-power-enable;
53		};
54	};
55
56	i2c1_default: i2c1_default {
57		group1 {
58			psels = <NRF_PSEL(TWIM_SDA, 0, 30)>,
59				<NRF_PSEL(TWIM_SCL, 0, 31)>;
60		};
61	};
62
63	i2c1_sleep: i2c1_sleep {
64		group1 {
65			psels = <NRF_PSEL(TWIM_SDA, 0, 30)>,
66				<NRF_PSEL(TWIM_SCL, 0, 31)>;
67			low-power-enable;
68		};
69	};
70
71	pwm0_default: pwm0_default {
72		group1 {
73			psels = <NRF_PSEL(PWM_OUT0, 0, 13)>;
74			nordic,invert;
75		};
76	};
77
78	pwm0_sleep: pwm0_sleep {
79		group1 {
80			psels = <NRF_PSEL(PWM_OUT0, 0, 13)>;
81			low-power-enable;
82		};
83	};
84
85	spi0_default: spi0_default {
86		group1 {
87			psels = <NRF_PSEL(SPIM_SCK, 0, 27)>,
88				<NRF_PSEL(SPIM_MOSI, 0, 26)>,
89				<NRF_PSEL(SPIM_MISO, 0, 29)>;
90		};
91	};
92
93	spi0_sleep: spi0_sleep {
94		group1 {
95			psels = <NRF_PSEL(SPIM_SCK, 0, 27)>,
96				<NRF_PSEL(SPIM_MOSI, 0, 26)>,
97				<NRF_PSEL(SPIM_MISO, 0, 29)>;
98			low-power-enable;
99		};
100	};
101
102	spi1_default: spi1_default {
103		group1 {
104			psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
105				<NRF_PSEL(SPIM_MOSI, 0, 30)>,
106				<NRF_PSEL(SPIM_MISO, 1, 8)>;
107		};
108	};
109
110	spi1_sleep: spi1_sleep {
111		group1 {
112			psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
113				<NRF_PSEL(SPIM_MOSI, 0, 30)>,
114				<NRF_PSEL(SPIM_MISO, 1, 8)>;
115			low-power-enable;
116		};
117	};
118
119	spi2_default: spi2_default {
120		group1 {
121			psels = <NRF_PSEL(SPIM_SCK, 0, 19)>,
122				<NRF_PSEL(SPIM_MOSI, 0, 20)>,
123				<NRF_PSEL(SPIM_MISO, 0, 21)>;
124		};
125	};
126
127	spi2_sleep: spi2_sleep {
128		group1 {
129			psels = <NRF_PSEL(SPIM_SCK, 0, 19)>,
130				<NRF_PSEL(SPIM_MOSI, 0, 20)>,
131				<NRF_PSEL(SPIM_MISO, 0, 21)>;
132			low-power-enable;
133		};
134	};
135
136	qspi_default: qspi_default {
137		group1 {
138			psels = <NRF_PSEL(QSPI_SCK, 0, 19)>,
139				<NRF_PSEL(QSPI_IO0, 0, 20)>,
140				<NRF_PSEL(QSPI_IO1, 0, 21)>,
141				<NRF_PSEL(QSPI_IO2, 0, 22)>,
142				<NRF_PSEL(QSPI_IO3, 0, 23)>,
143				<NRF_PSEL(QSPI_CSN, 0, 17)>;
144		};
145	};
146
147	qspi_sleep: qspi_sleep {
148		group1 {
149			psels = <NRF_PSEL(QSPI_SCK, 0, 19)>,
150				<NRF_PSEL(QSPI_IO0, 0, 20)>,
151				<NRF_PSEL(QSPI_IO1, 0, 21)>,
152				<NRF_PSEL(QSPI_IO2, 0, 22)>,
153				<NRF_PSEL(QSPI_IO3, 0, 23)>,
154				<NRF_PSEL(QSPI_CSN, 0, 17)>;
155			low-power-enable;
156		};
157	};
158
159	spi3_default: spi3_default {
160		group1 {
161			psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
162				<NRF_PSEL(SPIM_MISO, 1, 14)>,
163				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
164		};
165	};
166
167	spi3_sleep: spi3_sleep {
168		group1 {
169			psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
170				<NRF_PSEL(SPIM_MISO, 1, 14)>,
171				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
172			low-power-enable;
173		};
174	};
175
176};
177