1/*
2 * Copyright (c) 2022 Nordic Semiconductor
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	uart0_default: uart0_default {
8		group1 {
9			psels = <NRF_PSEL(UART_TX, 0, 6)>,
10				<NRF_PSEL(UART_RX, 0, 8)>,
11				<NRF_PSEL(UART_RTS, 0, 5)>,
12				<NRF_PSEL(UART_CTS, 0, 7)>;
13		};
14	};
15
16	uart0_sleep: uart0_sleep {
17		group1 {
18			psels = <NRF_PSEL(UART_TX, 0, 6)>,
19				<NRF_PSEL(UART_RX, 0, 8)>,
20				<NRF_PSEL(UART_RTS, 0, 5)>,
21				<NRF_PSEL(UART_CTS, 0, 7)>;
22			low-power-enable;
23		};
24	};
25
26	i2c1_default: i2c1_default {
27		group1 {
28			psels = <NRF_PSEL(TWIM_SDA, 0, 30)>,
29				<NRF_PSEL(TWIM_SCL, 0, 31)>;
30		};
31	};
32
33	i2c1_sleep: i2c1_sleep {
34		group1 {
35			psels = <NRF_PSEL(TWIM_SDA, 0, 30)>,
36				<NRF_PSEL(TWIM_SCL, 0, 31)>;
37			low-power-enable;
38		};
39	};
40
41	pwm0_default: pwm0_default {
42		group1 {
43			psels = <NRF_PSEL(PWM_OUT0, 0, 13)>;
44			nordic,invert;
45		};
46	};
47
48	pwm0_sleep: pwm0_sleep {
49		group1 {
50			psels = <NRF_PSEL(PWM_OUT0, 0, 13)>;
51			low-power-enable;
52		};
53	};
54
55	spi0_default: spi0_default {
56		group1 {
57			psels = <NRF_PSEL(SPIM_SCK, 0, 27)>,
58				<NRF_PSEL(SPIM_MOSI, 0, 26)>,
59				<NRF_PSEL(SPIM_MISO, 0, 29)>;
60		};
61	};
62
63	spi0_sleep: spi0_sleep {
64		group1 {
65			psels = <NRF_PSEL(SPIM_SCK, 0, 27)>,
66				<NRF_PSEL(SPIM_MOSI, 0, 26)>,
67				<NRF_PSEL(SPIM_MISO, 0, 29)>;
68			low-power-enable;
69		};
70	};
71
72	spi1_default: spi1_default {
73		group1 {
74			psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
75				<NRF_PSEL(SPIM_MOSI, 0, 30)>,
76				<NRF_PSEL(SPIM_MISO, 1, 8)>;
77		};
78	};
79
80	spi1_sleep: spi1_sleep {
81		group1 {
82			psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
83				<NRF_PSEL(SPIM_MOSI, 0, 30)>,
84				<NRF_PSEL(SPIM_MISO, 1, 8)>;
85			low-power-enable;
86		};
87	};
88
89	spi2_default: spi2_default {
90		group1 {
91			psels = <NRF_PSEL(SPIM_SCK, 0, 19)>,
92				<NRF_PSEL(SPIM_MOSI, 0, 20)>,
93				<NRF_PSEL(SPIM_MISO, 0, 21)>;
94		};
95	};
96
97	spi2_sleep: spi2_sleep {
98		group1 {
99			psels = <NRF_PSEL(SPIM_SCK, 0, 19)>,
100				<NRF_PSEL(SPIM_MOSI, 0, 20)>,
101				<NRF_PSEL(SPIM_MISO, 0, 21)>;
102			low-power-enable;
103		};
104	};
105
106	qspi_default: qspi_default {
107		group1 {
108			psels = <NRF_PSEL(QSPI_SCK, 0, 19)>,
109				<NRF_PSEL(QSPI_IO0, 0, 20)>,
110				<NRF_PSEL(QSPI_IO1, 0, 21)>,
111				<NRF_PSEL(QSPI_IO2, 0, 22)>,
112				<NRF_PSEL(QSPI_IO3, 0, 23)>,
113				<NRF_PSEL(QSPI_CSN, 0, 17)>;
114		};
115	};
116
117	qspi_sleep: qspi_sleep {
118		group1 {
119			psels = <NRF_PSEL(QSPI_SCK, 0, 19)>,
120				<NRF_PSEL(QSPI_IO0, 0, 20)>,
121				<NRF_PSEL(QSPI_IO1, 0, 21)>,
122				<NRF_PSEL(QSPI_IO2, 0, 22)>,
123				<NRF_PSEL(QSPI_IO3, 0, 23)>,
124				<NRF_PSEL(QSPI_CSN, 0, 17)>;
125			low-power-enable;
126		};
127	};
128
129};
130