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/Zephyr-latest/samples/modules/cmsis_dsp/moving_average/
Dsample.yaml7 - samples
9 - qemu_cortex_m0
10 - native_sim
12 - cmsis-dsp
17 - "Input\\[00\\]: 0 0 0 0 0 0 0 0 0 0 | Output\\[00\\]: 0.00"
18 - "Input\\[01\\]: 0 0 0 0 0 0 0 0 0 1 | Output\\[01\\]: 0.10"
19 - "Input\\[02\\]: 0 0 0 0 0 0 0 0 1 2 | Output\\[02\\]: 0.30"
20 - "Input\\[03\\]: 0 0 0 0 0 0 0 1 2 3 | Output\\[03\\]: 0.60"
21 - "Input\\[04\\]: 0 0 0 0 0 0 1 2 3 4 | Output\\[04\\]: 1.00"
22 - "Input\\[05\\]: 0 0 0 0 0 1 2 3 4 5 | Output\\[05\\]: 1.50"
[all …]
/Zephyr-latest/tests/lib/cmsis_dsp/filtering/src/
Dmisc_q15.c3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
52 DEFINE_CORRELATE_TEST(14, 16);
53 DEFINE_CORRELATE_TEST(14, 17);
57 DEFINE_CORRELATE_TEST(15, 16);
58 DEFINE_CORRELATE_TEST(15, 17);
61 DEFINE_CORRELATE_TEST(16, 15);
62 DEFINE_CORRELATE_TEST(16, 16);
63 DEFINE_CORRELATE_TEST(16, 17);
64 DEFINE_CORRELATE_TEST(16, 18);
[all …]
/Zephyr-latest/tests/subsys/display/cfb/basic/src/
Dprint_rectspace1016.c4 * SPDX-License-Identifier: Apache-2.0
49 if (font_width == 10 && font_height == 16) { in cfb_test_before()
72 zassert_true(verify_image_and_bg(0, 0, rectspace1016, 10, 16, 0)); in ZTEST()
80 zassert_true(verify_image_and_bg(1, 1, rectspace1016, 10, 16, 0)); in ZTEST()
91 zassert_true(verify_image_and_bg(9, 15, rectspace1016, 10, 16, 0)); in ZTEST()
96 zassert_ok(cfb_print(dev, " ", 10, 16)); in ZTEST()
99 zassert_true(verify_image_and_bg(10, 16, rectspace1016, 10, 16, 0)); in ZTEST()
104 zassert_ok(cfb_print(dev, " ", 11, 17)); in ZTEST()
107 zassert_true(verify_image_and_bg(11, 17, rectspace1016, 10, 16, 0)); in ZTEST()
119 zassert_true(verify_image_and_bg(0, 0, kerning_3_2rectspace1016, 23, 16, 0)); in ZTEST()
[all …]
Ddraw_text_rectspace1016.c4 * SPDX-License-Identifier: Apache-2.0
49 if (font_width == 10 && font_height == 16) { in cfb_test_before()
72 zassert_true(verify_image_and_bg(0, 0, rectspace1016, 10, 16, 0)); in ZTEST()
80 zassert_true(verify_image_and_bg(1, 1, rectspace1016, 10, 16, 0)); in ZTEST()
91 zassert_true(verify_image_and_bg(9, 15, rectspace1016, 10, 16, 0)); in ZTEST()
96 zassert_ok(cfb_draw_text(dev, " ", 10, 16)); in ZTEST()
99 zassert_true(verify_image_and_bg(10, 16, rectspace1016, 10, 16, 0)); in ZTEST()
104 zassert_ok(cfb_draw_text(dev, " ", 11, 17)); in ZTEST()
107 zassert_true(verify_image_and_bg(11, 17, rectspace1016, 10, 16, 0)); in ZTEST()
119 zassert_true(verify_image_and_bg(0, 0, kerning_3_2rectspace1016, 23, 16, 0)); in ZTEST()
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-r8a77951.h4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
45 #define PIN_A16 RCAR_GP_PIN(1, 16)
46 #define PIN_A17 RCAR_GP_PIN(1, 17)
105 #define PIN_SD3_DATA7 RCAR_GP_PIN(4, 16)
106 #define PIN_SD3_DS RCAR_GP_PIN(4, 17)
123 #define PIN_HRTS0 RCAR_GP_PIN(5, 16)
124 #define PIN_MSIOF0_SCK RCAR_GP_PIN(5, 17)
149 #define PIN_SSI_SDATA6 RCAR_GP_PIN(6, 16)
[all …]
Dpinctrl-r8a77961.h3 * Copyright (c) 2023-2024 EPAM Systems
5 * SPDX-License-Identifier: Apache-2.0
10 #include "pinctrl-rcar-common.h"
13 #define PIN_NONE -1
46 #define PIN_A16 RCAR_GP_PIN(1, 16)
47 #define PIN_A17 RCAR_GP_PIN(1, 17)
106 #define PIN_SD3_DATA7 RCAR_GP_PIN(4, 16)
107 #define PIN_SD3_DS RCAR_GP_PIN(4, 17)
124 #define PIN_HRTS0 RCAR_GP_PIN(5, 16)
125 #define PIN_MSIOF0_SCK RCAR_GP_PIN(5, 17)
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/Zephyr-latest/tests/subsys/dsp/basicmath/src/
Dq15.c3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
19 #define ABS_ERROR_THRESH_Q63 ((q63_t)(1 << 17))
48 DEFINE_TEST_VARIANT4(basic_math_q15, zdsp_add_q15, 16, in_com1, in_com2, ref_add, 16);
51 17);
53 17);
84 DEFINE_TEST_VARIANT4(basic_math_q15, zdsp_add_q15_in_place, 16, in_com1, in_com2, ref_add, 16);
87 ref_add_possat, 17);
89 ref_add_negsat, 17);
120 DEFINE_TEST_VARIANT4(basic_math_q15, zdsp_sub_q15, 16, in_com1, in_com2, ref_sub, 16);
[all …]
/Zephyr-latest/samples/userspace/shared_mem/src/
Dmain.h4 * SPDX-License-Identifier: Apache-2.0
54 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25}
55 #define START_WHEEL2 {6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, \
56 17, 18, 19, 20, 21, 22, 23, 24, 25, 5, 0, 4, 1, 3, 2}
58 15, 14, 17, 16, 19, 18, 21, 20, 23, 22, 25, 24}
/Zephyr-latest/subsys/net/lib/lwm2m/
Ducifi_lpwan.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Mandatory resource: ID 6 - IEEE MAC address of the device (up to 64 bits) */
11 #define MAC_ADDRESS_SIZE 17 /* 16 hex digits, eg. "01a2b3c4d5e6f708\0" */
14 /* clang-format off */
30 #define UCIFI_LPWAN_MAX_REPEAT_TIME_RID 16
31 #define UCIFI_LPWAN_NUMBER_REPEATS_RID 17
39 /* clang-format on */
/Zephyr-latest/dts/bindings/pinctrl/
Dite,it8xxx2-pinctrl-func.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
32 volt-sel:
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Dsifive,pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
12 - SIFIVE_PINMUX_IOF0
13 - SIFIVE_PINMUX_IOF1
15 For example, setting pins 16 and 17 both to IOF0 would look like this:
17 #include <dt-bindings/pinctrl/sifive-pinctrl.h>
21 pinmux = <16 SIFIVE_PINMUX_IOF0>;
24 pinmux = <17 SIFIVE_PINMUX_IOF0>;
36 child-binding:
/Zephyr-latest/soc/intel/apollo_lake/
Dsoc_gpio.h2 * Copyright (c) 2018-2019, Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
39 #define APL_GPIO_16 16
40 #define APL_GPIO_17 17
73 #define APL_GPIO_48 16
74 #define APL_GPIO_49 17
123 #define APL_GPIO_203 16
124 #define APL_GPIO_204 17
157 #define APL_GPIO_88 16
158 #define APL_GPIO_89 17
[all …]
/Zephyr-latest/dts/arm/microchip/
Dmec172x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "microchip,xec-pcr";
13 reg-names = "pcrr", "vbatr";
15 core-clock-div = <1>;
17 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
18 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
19 clk32kmon-period-min = <1435>;
20 clk32kmon-period-max = <1495>;
21 clk32kmon-duty-cycle-var-max = <132>;
22 clk32kmon-valid-min = <4>;
[all …]
/Zephyr-latest/drivers/ethernet/
Deth_dwmac_priv.h6 * SPDX-License-Identifier: Apache-2.0
10 * DesignWare Cores Ethernet Quality-of-Service Databook
76 #define REG_READ(r) sys_read32(p->base_addr + (r))
77 #define REG_WRITE(r, v) sys_write32((v), p->base_addr + (r))
107 #define MAC_CONF_JD BIT(17)
108 #define MAC_CONF_JE BIT(16)
133 #define MAC_EXT_CONF_SPEN BIT(17)
134 #define MAC_EXT_CONF_DCRCC BIT(16)
144 #define MAC_PKT_FILTER_VTFE BIT(16)
185 #define MAC_VLAN_TAG_CTRL_VTIM BIT(17)
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Desp32c3-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
45 #define I2C0_SCL_GPIO16 ESP32_PINMUX(16, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
47 #define I2C0_SCL_GPIO17 ESP32_PINMUX(17, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
90 #define I2C0_SDA_GPIO16 ESP32_PINMUX(16, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
92 #define I2C0_SDA_GPIO17 ESP32_PINMUX(17, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
135 #define I2S_I_BCK_GPIO16 ESP32_PINMUX(16, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT)
137 #define I2S_I_BCK_GPIO17 ESP32_PINMUX(17, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT)
180 #define I2S_I_SD_GPIO16 ESP32_PINMUX(16, ESP_I2SI_SD_IN, ESP_NOSIG)
182 #define I2S_I_SD_GPIO17 ESP32_PINMUX(17, ESP_I2SI_SD_IN, ESP_NOSIG)
225 #define I2S_I_WS_GPIO16 ESP32_PINMUX(16, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT)
[all …]
Drenesas-rzt2m-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
10 #define RZT2M_PINMUX(port, pin, func) ((port << 16) | (pin << 8) | func)
12 #define UART0TX_P16_5 RZT2M_PINMUX(16, 5, 1)
13 #define UART0RX_P16_6 RZT2M_PINMUX(16, 6, 2)
16 #define UART3RX_P17_7 RZT2M_PINMUX(17, 7, 4)
Desp32c6-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
62 ESP32_PINMUX(16, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
65 ESP32_PINMUX(17, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
135 ESP32_PINMUX(16, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
138 ESP32_PINMUX(17, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
191 #define LEDC_CH0_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
193 #define LEDC_CH0_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
240 #define LEDC_CH1_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
242 #define LEDC_CH1_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
289 #define LEDC_CH2_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
[all …]
/Zephyr-latest/drivers/can/
Dcan_mcp251xfd.h5 * SPDX-License-Identifier: Apache-2.0
46 #define MCP251XFD_RX_FIFO_SIZE_MAX (MCP251XFD_RAM_SIZE - MCP251XFD_RX_FIFO_START_ADDR)
84 /* MPC251x registers - mostly copied from Linux kernel implementation of driver */
103 #define MCP251XFD_REG_CON_ESIGM BIT(17)
104 #define MCP251XFD_REG_CON_RTXAT BIT(16)
122 #define MCP251XFD_REG_NBTCFG_TSEG1_MASK GENMASK(23, 16)
128 #define MCP251XFD_REG_DBTCFG_TSEG1_MASK GENMASK(20, 16)
135 #define MCP251XFD_REG_TDC_TDCMOD_MASK GENMASK(17, 16)
141 #define MCP251XFD_REG_TDC_TDCO_MIN -64
148 #define MCP251XFD_REG_TSCON_TSEOF BIT(17)
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/Zephyr-latest/dts/bindings/sensor/
Dbosch,bmp388.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 200 - 200 - 5ms (default; chip reset value)
17 100 - 100 - 10ms
18 50 - 50 - 20ms
19 25 - 25 - 40ms
20 12.5 - 25/2 - 80ms
21 6.25 - 25/4 - 160ms
[all …]
Dbosch,bmp390.yaml3 # SPDX-License-Identifier: Apache-2.0
7 include: sensor-device.yaml
10 int-gpios:
11 type: phandle-array
17 200 - 200 - 5ms (default; chip reset value)
18 100 - 100 - 10ms
19 50 - 50 - 20ms
20 25 - 25 - 40ms
21 12.5 - 25/2 - 80ms
22 6.25 - 25/4 - 160ms
[all …]
/Zephyr-latest/tests/drivers/rtc/shell/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
61 get_time_mock.rtc.tm_year = 2023 - 1900; /* rtc_time year offset */ in configure_get_time_mock()
62 get_time_mock.rtc.tm_mon = 12 - 1; /* rtc_time month offset */ in configure_get_time_mock()
79 zassert_equal(year, rtctime->tm_year + 1900, "Year mismatch"); in assert_set_time()
80 zassert_equal(mon, rtctime->tm_mon + 1, "Month mismatch"); in assert_set_time()
81 zassert_equal(mday, rtctime->tm_mday, "Day mismatch"); in assert_set_time()
82 zassert_equal(hour, rtctime->tm_hour, "Hour mismatch"); in assert_set_time()
83 zassert_equal(min, rtctime->tm_min, "Minute mismatch"); in assert_set_time()
84 zassert_equal(sec, rtctime->tm_sec, "Second mismatch"); in assert_set_time()
104 configure_get_time_mock(-ENODATA); in ZTEST()
[all …]
/Zephyr-latest/boards/actinius/icarus_som_dk/
Darduino_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpio0 15 0>, /* A0 */
14 <1 0 &gpio0 16 0>, /* A1 */
15 <2 0 &gpio0 17 0>, /* A2 */
29 <16 0 &gpio0 7 0>, /* D10 */
30 <17 0 &gpio0 13 0>, /* D11 */
[all …]
/Zephyr-latest/soc/xlnx/zynq7000/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
89 #define MIO_PIN_SPECIAL_MASK_SDIO0_CD GENMASK(21, 16)
90 #define MIO_PIN_SPECIAL_SHIFT_SDIO0_CD 16
99 #define MIO_PIN_SPECIAL_MASK_SDIO1_CD GENMASK(21, 16)
100 #define MIO_PIN_SPECIAL_SHIFT_SDIO1_CD 16
124 #define MIO16 16
125 #define MIO17 17
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
172 #define MIO_GROUP_SPI0_0_GRP_PINS 16, 17, 21
[all …]
/Zephyr-latest/samples/kernel/condition_variables/simple/
DREADME.rst26 .. zephyr-app-commands::
27 :zephyr-app: samples/kernel/condition_variables/simple
28 :host-os: unix
38 .. code-block:: console
56 [thread 16] working (0/5)
57 [thread 17] working (0/5)
76 [thread 16] working (1/5)
77 [thread 17] working (1/5)
97 [thread 16] working (2/5)
98 [thread 17] working (2/5)
[all …]
/Zephyr-latest/drivers/pinctrl/renesas/rcar/
Dpfc_r8a779f0.c4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f0.h>
18 { RCAR_GP_PIN(0, 4), 16, 3 }, /* HCTS0_N */
29 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF0_RXD */
37 { RCAR_GP_PIN(0, 20), 16, 3 }, /* IRQ3 */
40 { RCAR_GP_PIN(0, 17), 4, 3 }, /* IRQ0 */
41 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF0_SS2 */
49 { RCAR_GP_PIN(1, 4), 16, 3 }, /* GP1_04 */
60 { RCAR_GP_PIN(1, 12), 16, 3 }, /* MMC_SD_CLK */
71 { RCAR_GP_PIN(1, 20), 16, 3 }, /* MMC_DS */
[all …]

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