Lines Matching +full:16 +full:- +full:17
4 * SPDX-License-Identifier: Apache-2.0
89 #define MIO_PIN_SPECIAL_MASK_SDIO0_CD GENMASK(21, 16)
90 #define MIO_PIN_SPECIAL_SHIFT_SDIO0_CD 16
99 #define MIO_PIN_SPECIAL_MASK_SDIO1_CD GENMASK(21, 16)
100 #define MIO_PIN_SPECIAL_SHIFT_SDIO1_CD 16
124 #define MIO16 16
125 #define MIO17 17
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
172 #define MIO_GROUP_SPI0_0_GRP_PINS 16, 17, 21
200 #define MIO_GROUP_SDIO0_0_GRP_PINS 16, 17, 18, 19, 20, 21
212 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
217 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23
231 #define MIO_GROUP_CAN1_2_GRP_PINS 16, 17
254 #define MIO_GROUP_UART1_2_GRP_PINS 16, 17
276 #define MIO_GROUP_I2C1_1_GRP_PINS 16, 17
289 #define MIO_GROUP_TTC1_0_GRP_PINS 16, 17
313 #define MIO_GROUP_GPIO0_16_GRP_PINS 16
314 #define MIO_GROUP_GPIO0_17_GRP_PINS 17
360 /* Iterate over each pinctrl-n phandle child */
367 * - Iterate over each pin in group and populate pinctrl_soc_pin_t
369 * - Iterate over each pin in pins and populate pinctrl_soc_pin_t