| /Zephyr-latest/samples/modules/cmsis_dsp/moving_average/ |
| D | sample.yaml | 7 - samples
9 - qemu_cortex_m0
10 - native_sim
12 - cmsis-dsp
17 - "Input\\[00\\]: 0 0 0 0 0 0 0 0 0 0 | Output\\[00\\]: 0.00"
18 - "Input\\[01\\]: 0 0 0 0 0 0 0 0 0 1 | Output\\[01\\]: 0.10"
19 - "Input\\[02\\]: 0 0 0 0 0 0 0 0 1 2 | Output\\[02\\]: 0.30"
20 - "Input\\[03\\]: 0 0 0 0 0 0 0 1 2 3 | Output\\[03\\]: 0.60"
21 - "Input\\[04\\]: 0 0 0 0 0 0 1 2 3 4 | Output\\[04\\]: 1.00"
22 - "Input\\[05\\]: 0 0 0 0 0 1 2 3 4 5 | Output\\[05\\]: 1.50"
[all …]
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| /Zephyr-latest/soc/intel/apollo_lake/ |
| D | soc_gpio.h | 2 * Copyright (c) 2018-2019, Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
34 #define APL_GPIO_11 11
49 #define APL_GPIO_26 26
68 #define APL_GPIO_43 11
83 #define APL_GPIO_70 26
102 #define APL_GPIO_SVID0_ALERT_B 11
118 #define APL_GPIO_198 11
133 #define APL_GPIO_213 26
152 #define APL_GPIO_83 11
[all …]
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| /Zephyr-latest/samples/sensor/isl29035/boards/ |
| D | nrf52dk_nrf52832.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 &i2c0 { /* SDA P0.26, SCL P0.27, ALERT P1.11 */
11 int-gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
|
| /Zephyr-latest/samples/sensor/adt7420/boards/ |
| D | nrf52dk_nrf52832.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 &i2c0 { /* SDA P0.26, SCL P0.27, ALERT P0.11 */
9 clock-frequency = <I2C_BITRATE_STANDARD>;
13 int-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
|
| /Zephyr-latest/soc/microchip/mec/mec172x/reg/ |
| D | mec172x_ecia.h | 4 * SPDX-License-Identifier: Apache-2.0
17 #define MCHP_LAST_GIRQ_NOS 26u
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
27 BIT(26))
33 #define MCHP_ECIA_ALL_BITMAP GENMASK(26, 8)
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
58 * BLOCK_ACTIVE registers: GIRQ8 is bit[8], ..., GIRQ26 is bit[26].
60 * Each GIRQ is composed of 5 32-bit registers.
[all …]
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | renesas,mipi-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 This binding provides a mapping for the default 26 pins as depicted below:
21 11 MIPI_CL_N 3V3 24
23 13 GND 5V0 26
25 compatible: "renesas,ra-gpio-mipi-header"
27 include: [gpio-nexus.yaml, base.yaml]
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| D | raspberrypi,pico-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 This binding provides a nexus mapping for the default 26 pins as depicted below:
11 0 GPIO0/UART0_TX VBUS -
12 1 GPIO1/UART0_RX VSYS -
13 - GND GND -
14 2 GPIO2 3V3_EN -
15 3 GPIO3 3V3_OUT -
16 4 GPIO4/I2C0_SDA ADC_VREF -
18 - GND GND -
20 7 GPIO7 GPIO26/ADC0 26
[all …]
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| /Zephyr-latest/soc/microchip/mec/common/ |
| D | soc_pins.h | 4 * SPDX-License-Identifier: Apache-2.0
26 #define MCHP_GPIO_013 (11U)
41 #define MCHP_GPIO_032 (26U)
60 #define MCHP_GPIO_053 (11U)
75 #define MCHP_GPIO_072 (26U)
94 #define MCHP_GPIO_113 (11U)
109 #define MCHP_GPIO_132 (26U)
128 #define MCHP_GPIO_153 (11U)
143 #define MCHP_GPIO_172 (26U)
162 #define MCHP_GPIO_213 (11U)
[all …]
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| /Zephyr-latest/include/zephyr/dt-bindings/reset/ |
| D | npcx4_reset.h | 4 * SPDX-License-Identifier: Apache-2.0
26 #define NPCX_RESET_GPIOB (NPCX_RESET_SWRST_CTL1_OFFSET + 11)
39 #define NPCX_RESET_MIWU0 (NPCX_RESET_SWRST_CTL1_OFFSET + 26)
55 #define NPCX_RESET_SMB3 (NPCX_RESET_SWRST_CTL2_OFFSET + 11)
70 #define NPCX_RESET_MFT16_3 (NPCX_RESET_SWRST_CTL2_OFFSET + 26)
86 #define NPCX_RESET_PMCH2 (NPCX_RESET_SWRST_CTL3_OFFSET + 11)
98 #define NPCX_RESET_SHA_2B (NPCX_RESET_SWRST_CTL3_OFFSET + 26)
106 #define NPCX_RESET_MDMA3 (NPCX_RESET_SWRST_CTL4_OFFSET + 26)
|
| D | npcx9_reset.h | 4 * SPDX-License-Identifier: Apache-2.0
26 #define NPCX_RESET_GPIOB (NPCX_RESET_SWRST_CTL1_OFFSET + 11)
39 #define NPCX_RESET_MIWU0 (NPCX_RESET_SWRST_CTL1_OFFSET + 26)
54 #define NPCX_RESET_SMB3 (NPCX_RESET_SWRST_CTL2_OFFSET + 11)
69 #define NPCX_RESET_MFT16_3 (NPCX_RESET_SWRST_CTL2_OFFSET + 26)
82 #define NPCX_RESET_PMCH2 (NPCX_RESET_SWRST_CTL3_OFFSET + 11)
98 #define NPCX_RESET_MDMA3 (NPCX_RESET_SWRST_CTL4_OFFSET + 26)
|
| D | npcx7_reset.h | 4 * SPDX-License-Identifier: Apache-2.0
25 #define NPCX_RESET_GPIOB (NPCX_RESET_SWRST_CTL1_OFFSET + 11)
39 #define NPCX_RESET_MIWU0 (NPCX_RESET_SWRST_CTL1_OFFSET + 26)
54 #define NPCX_RESET_SMB3 (NPCX_RESET_SWRST_CTL2_OFFSET + 11)
69 #define NPCX_RESET_MFT16_3 (NPCX_RESET_SWRST_CTL2_OFFSET + 26)
81 #define NPCX_RESET_PMCH2 (NPCX_RESET_SWRST_CTL3_OFFSET + 11)
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| /Zephyr-latest/boards/ezurio/pinnacle_100_dvk/ |
| D | pinnacle_100_dvk-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
22 low-power-enable;
41 low-power-enable;
47 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
54 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
56 low-power-enable;
63 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
71 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
73 low-power-enable;
79 psels = <NRF_PSEL(SPIM_SCK, 0, 11)>,
[all …]
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| /Zephyr-latest/soc/xlnx/zynq7000/common/ |
| D | pinctrl_soc.h | 4 * SPDX-License-Identifier: Apache-2.0
25 #define MIO_PIN_IO_TYPE_MASK GENMASK(11, 9)
119 #define MIO11 11
134 #define MIO26 26
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
169 #define MIO_GROUP_QSPI1_0_GRP_PINS 9, 10, 11, 12, 13
184 #define MIO_GROUP_SPI1_0_GRP_PINS 10, 11, 12
190 #define MIO_GROUP_SPI1_1_SS1_PINS 26
203 #define MIO_GROUP_SDIO1_0_GRP_PINS 10, 11, 12, 13, 14, 15
[all …]
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | rpi-pico-rp2350-pinctrl-common.h | 4 * SPDX-License-Identifier: Apache-2.0
15 #define RP2_PINCTRL_GPIO_FUNC_UART_AUX 11
18 #include "rpi-pico-pinctrl-common.h"
31 #define PIO2_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PIO2)
46 #define PIO2_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PIO2)
61 #define UART1_RX_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_UART_ALT)
68 #define UART1_TX_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_UART_ALT)
|
| D | esp32-pinctrl.h | 4 * SPDX-License-Identifier: Apache-2.0
18 ESP32_PINMUX(26, ESP_NOSIG, ESP_DAC2_OUT)
55 ESP32_PINMUX(11, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
97 ESP32_PINMUX(26, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
143 ESP32_PINMUX(11, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
185 ESP32_PINMUX(26, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
231 ESP32_PINMUX(11, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
273 ESP32_PINMUX(26, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
319 ESP32_PINMUX(11, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
361 ESP32_PINMUX(26, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
[all …]
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| D | rpi-pico-pinctrl-common.h | 5 * SPDX-License-Identifier: Apache-2.0
24 /* These function are common. SoC-specific functions are defined in their
48 #define SPI1_TX_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_SPI)
63 #define SPI1_SCK_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_SPI)
79 #define UART1_RTS_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_UART)
94 #define UART1_CTS_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_UART)
110 #define I2C1_SCL_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_I2C)
125 #define I2C1_SDA_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_I2C)
141 #define PWM_5B_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PWM)
156 #define PWM_5A_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PWM)
[all …]
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| /Zephyr-latest/boards/circuitdojo/feather/ |
| D | circuitdojo_feather_nrf9160_common-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
18 low-power-enable;
33 low-power-enable;
48 low-power-enable;
54 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
61 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
63 low-power-enable;
76 low-power-enable;
82 psels = <NRF_PSEL(SPIM_SCK, 0, 11)>,
90 psels = <NRF_PSEL(SPIM_SCK, 0, 11)>,
[all …]
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| /Zephyr-latest/boards/actinius/icarus/ |
| D | actinius_icarus_common-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
18 low-power-enable;
33 low-power-enable;
39 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
46 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
48 low-power-enable;
65 low-power-enable;
72 <NRF_PSEL(PWM_OUT1, 0, 11)>,
81 <NRF_PSEL(PWM_OUT1, 0, 11)>,
83 low-power-enable;
|
| /Zephyr-latest/boards/sparkfun/thing_plus/ |
| D | sparkfun_thing_plus_nrf9160_common-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
18 low-power-enable;
33 low-power-enable;
48 low-power-enable;
54 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
61 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
63 low-power-enable;
77 low-power-enable;
83 psels = <NRF_PSEL(SPIM_SCK, 0, 11)>,
91 psels = <NRF_PSEL(SPIM_SCK, 0, 11)>,
[all …]
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| /Zephyr-latest/boards/phytec/reel_board/dts/ |
| D | reel_board-pinctrl.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
14 bias-pull-up;
22 low-power-enable;
37 low-power-enable;
43 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
50 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
52 low-power-enable;
61 psels = <NRF_PSEL(PWM_OUT1, 0, 11)>,
71 <NRF_PSEL(PWM_OUT1, 0, 11)>,
74 low-power-enable;
[all …]
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| /Zephyr-latest/include/zephyr/dt-bindings/gpio/ |
| D | microchip-xec-gpio.h | 4 * SPDX-License-Identifier: Apache-2.0
39 #define MCHP_GPIO_DECODE_013 XEC_GPIO_HELPER(&gpio_000_036, 11)
54 #define MCHP_GPIO_DECODE_032 XEC_GPIO_HELPER(&gpio_000_036, 26)
72 #define MCHP_GPIO_DECODE_053 XEC_GPIO_HELPER(&gpio_040_076, 11)
87 #define MCHP_GPIO_DECODE_072 XEC_GPIO_HELPER(&gpio_040_076, 26)
105 #define MCHP_GPIO_DECODE_113 XEC_GPIO_HELPER(&gpio_100_136, 11)
120 #define MCHP_GPIO_DECODE_132 XEC_GPIO_HELPER(&gpio_100_136, 26)
138 #define MCHP_GPIO_DECODE_153 XEC_GPIO_HELPER(&gpio_140_176, 11)
153 #define MCHP_GPIO_DECODE_172 XEC_GPIO_HELPER(&gpio_140_176, 26)
171 #define MCHP_GPIO_DECODE_213 XEC_GPIO_HELPER(&gpio_200_236, 11)
[all …]
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| /Zephyr-latest/dts/x86/intel/ |
| D | apollo_lake.dtsi | 2 * Copyright (c) 2017-2019 Intel Corporation.
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,apollo-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
[all …]
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| /Zephyr-latest/dts/arm/microchip/ |
| D | mec172x_common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "microchip,xec-pcr";
13 reg-names = "pcrr", "vbatr";
15 core-clock-div = <1>;
17 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
18 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
19 clk32kmon-period-min = <1435>;
20 clk32kmon-period-max = <1495>;
21 clk32kmon-duty-cycle-var-max = <132>;
22 clk32kmon-valid-min = <4>;
[all …]
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| /Zephyr-latest/boards/nordic/nrf9151dk/ |
| D | nrf9151dk_nrf9151_common-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
13 psels = <NRF_PSEL(UART_RX, 0, 26)>,
15 bias-pull-up;
22 <NRF_PSEL(UART_RX, 0, 26)>,
25 low-power-enable;
37 bias-pull-up;
47 low-power-enable;
62 low-power-enable;
75 low-power-enable;
83 <NRF_PSEL(SPIM_MOSI, 0, 11)>;
[all …]
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| /Zephyr-latest/boards/nordic/nrf9161dk/ |
| D | nrf9161dk_nrf9161_common-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
13 psels = <NRF_PSEL(UART_RX, 0, 26)>,
15 bias-pull-up;
22 <NRF_PSEL(UART_RX, 0, 26)>,
25 low-power-enable;
37 bias-pull-up;
47 low-power-enable;
62 low-power-enable;
75 low-power-enable;
83 <NRF_PSEL(SPIM_MOSI, 0, 11)>;
[all …]
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