Lines Matching +full:11 +full:- +full:26
4 * SPDX-License-Identifier: Apache-2.0
17 #define MCHP_LAST_GIRQ_NOS 26u
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
27 BIT(26))
33 #define MCHP_ECIA_ALL_BITMAP GENMASK(26, 8)
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
58 * BLOCK_ACTIVE registers: GIRQ8 is bit[8], ..., GIRQ26 is bit[26].
60 * Each GIRQ is composed of 5 32-bit registers.
63 * +08h = Read-Only Result = Source AND Enable-Set
69 * 0x200: BLOCK_EN_SET bit == 1 connects bit-wise OR of all GIRQn result
71 * bit[8]=GIRQ8, bit[9]=GIRQ9, ..., bit[26]=GIRQ26
72 * 0x204: BLOCK_EN_CLR bit == 1 disconnects bit-wise OR of GIRQn source
74 * 0x208: BLOCK_ACTIVE (read-only)
77 * bit[26]=GIRQ26 has at least one source bit enabled and active.
78 * The aggregated (bit-wise OR) of GIRQ08, ..., GIRQ26 are connected to NVIC
80 * wake. If GIRQ22 sources are enabled activity on a source will re-enable the
85 * re-enter deep sleep.
87 * GIRQ08 -> NVIC 0
88 * GIRQ09 -> NVIC 1
90 * GIRQ21 -> NVIC 13
92 * GIRQ23 -> NVIC 14
94 * GIRQ26 -> NVIC 17
96 * Result bits in GIRQ's 13 - 21, and 23 can be directly connected to NVIC
162 #define MCHP_GPIO_0153_GIRQ_POS 11
174 #define MCHP_GPIO_0172_GIRQ_POS 26
190 #define MCHP_GPIO_0153_GIRQ_BIT BIT(11)
202 #define MCHP_GPIO_0172_GIRQ_BIT BIT(26)
220 #define MCHP_GPIO_0113_GIRQ_POS 11
235 #define MCHP_GPIO_0132_GIRQ_POS 26
251 #define MCHP_GPIO_0113_GIRQ_BIT BIT(11)
266 #define MCHP_GPIO_0132_GIRQ_BIT BIT(26)
284 #define MCHP_GPIO_0053_GIRQ_POS 11
299 #define MCHP_GPIO_0072_GIRQ_POS 26
316 #define MCHP_GPIO_0053_GIRQ_BIT BIT(11)
331 #define MCHP_GPIO_0072_GIRQ_BIT BIT(26)
350 #define MCHP_GPIO_0013_GIRQ_POS 11
365 #define MCHP_GPIO_0032_GIRQ_POS 26
382 #define MCHP_GPIO_0013_GIRQ_BIT BIT(11)
397 #define MCHP_GPIO_0032_GIRQ_BIT BIT(26)
416 #define MCHP_GPIO_0213_GIRQ_POS 11
431 #define MCHP_GPIO_0232_GIRQ_POS 26
448 #define MCHP_GPIO_0213_GIRQ_BIT BIT(11)
463 #define MCHP_GPIO_0232_GIRQ_BIT BIT(26)
499 #define MCHP_DMA_CH11_GIRQ_POS 11
516 #define MCHP_DMA_CH11_GIRQ_BIT BIT(11)
538 #define MCHP_ACPI_EC_3_IBF_GIRQ_POS 11
561 #define MCHP_ACPI_EC_3_IBF_GIRQ_BIT BIT(11)
609 #define MCHP_RCID_1_GIRQ_POS 11
629 #define MCHP_RCID_1_GIRQ_BIT BIT(11)
688 #define MCHP_CCT_0_CAP5_GIRQ_POS 26
708 #define MCHP_CCT_0_CAP5_GIRQ_BIT BIT(26)
752 #define MCHP_ESPI_SAF_CACHE_GIRQ_POS 11
765 #define MCHP_ESPI_SAF_CACHE_GIRQ_BIT BIT(11)
772 #define MCHP_GIRQ19_NVIC_AGGR 11u
822 #define MCHP_VCI_IN0_GIRQ_POS 11
830 #define MCHP_GLUE_GIRQ_POS 26
841 #define MCHP_VCI_IN0_GIRQ_BIT BIT(11)
849 #define MCHP_GLUE_GIRQ_BIT BIT(26)
917 #define MCHP_RTMR_0_SWI0_GIRQ_POS 11
935 #define MCHP_RTMR_0_SWI0_GIRQ_BIT BIT(11)
980 #define MCHP_MSVW02_SRC3_GIRQ_POS 11
995 #define MCHP_MSVW06_SRC2_GIRQ_POS 26
1009 #define MCHP_MSVW02_SRC3_GIRQ_BIT BIT(11)
1024 #define MCHP_MSVW06_SRC2_GIRQ_BIT BIT(26)
1050 #define MCHP_MSVW09_SRC3_GIRQ_POS 11
1067 #define MCHP_MSVW09_SRC3_GIRQ_BIT BIT(11)
1120 #define MCHP_GIRQ_LAST_NUM 26u
1121 #define MCHP_GIRQ_IDX(girq) ((uint32_t)(girq) - 8u)
1124 /* Number of NVIC Enable_Set/Clr, Pending_Set/Clr, Active 32-bit registers */
1159 uint8_t RSVD2[(0x0200 - 0x017c)];
1168 uint8_t RSVD2[(0x200 - 0x17c)];
1184 ecia->BLK_EN_SET = BIT(girq); in mchp_soc_ecia_girq_aggr_en()
1186 ecia->BLK_EN_CLR = BIT(girq); in mchp_soc_ecia_girq_aggr_en()
1199 ecia->GIRQ[girq - 8u].SRC = BIT(pin); in mchp_soc_ecia_girq_src_clr()
1211 ecia->GIRQ[girq - 8u].SRC = bitmap; in mchp_soc_ecia_girq_src_clr_bitmap()
1223 ecia->GIRQ[girq - 8u].EN_CLR = BIT(pin); in mchp_soc_ecia_girq_src_dis()
1235 ecia->GIRQ[girq - 8u].EN_SET = BIT(pin); in mchp_soc_ecia_girq_src_en()
1246 return ecia->GIRQ[girq - 8u].RESULT; in mchp_soc_ecia_girq_result()