Lines Matching +full:11 +full:- +full:26
4 * SPDX-License-Identifier: Apache-2.0
25 #define MIO_PIN_IO_TYPE_MASK GENMASK(11, 9)
119 #define MIO11 11
134 #define MIO26 26
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
169 #define MIO_GROUP_QSPI1_0_GRP_PINS 9, 10, 11, 12, 13
184 #define MIO_GROUP_SPI1_0_GRP_PINS 10, 11, 12
190 #define MIO_GROUP_SPI1_1_SS1_PINS 26
203 #define MIO_GROUP_SDIO1_0_GRP_PINS 10, 11, 12, 13, 14, 15
204 #define MIO_GROUP_SDIO1_1_GRP_PINS 22, 23, 24, 25, 26, 27
211 #define MIO_GROUP_SMC0_NOR_PINS 0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, \
212 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
216 #define MIO_GROUP_SMC0_NAND_PINS 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, \
218 #define MIO_GROUP_CAN0_0_GRP_PINS 10, 11
222 #define MIO_GROUP_CAN0_4_GRP_PINS 26, 27
241 #define MIO_GROUP_UART0_0_GRP_PINS 10, 11
245 #define MIO_GROUP_UART0_4_GRP_PINS 26, 27
264 #define MIO_GROUP_I2C0_0_GRP_PINS 10, 11
268 #define MIO_GROUP_I2C0_4_GRP_PINS 26, 27
293 #define MIO_GROUP_SWDT0_1_GRP_PINS 26, 27
308 #define MIO_GROUP_GPIO0_11_GRP_PINS 11
323 #define MIO_GROUP_GPIO0_26_GRP_PINS 26
360 /* Iterate over each pinctrl-n phandle child */
367 * - Iterate over each pin in group and populate pinctrl_soc_pin_t
369 * - Iterate over each pin in pins and populate pinctrl_soc_pin_t