| /Zephyr-Core-2.7.6/drivers/display/ |
| D | mb_font.c | 19 MB_IMAGE({ 0, 1, 0, 0, 0 },
20 { 0, 1, 0, 0, 0 },
21 { 0, 1, 0, 0, 0 },
23 { 0, 1, 0, 0, 0 }),
25 MB_IMAGE({ 0, 1, 0, 1, 0 },
26 { 0, 1, 0, 1, 0 },
31 MB_IMAGE({ 0, 1, 0, 1, 0 },
32 { 1, 1, 1, 1, 1 },
33 { 0, 1, 0, 1, 0 },
34 { 1, 1, 1, 1, 1 },
[all …]
|
| /Zephyr-Core-2.7.6/samples/bluetooth/mesh_demo/src/ |
| D | microbit.c | 29 #define SEQ_PAGE (NRF_FICR->CODEPAGESIZE * (NRF_FICR->CODESIZE - 1))
124 if (str[1] == '#') { in board_play_tune()
148 MB_IMAGE({ 1, 1, 1, 1, 1 }, in board_heartbeat()
149 { 1, 1, 1, 1, 1 }, in board_heartbeat()
150 { 1, 1, 1, 1, 1 }, in board_heartbeat()
151 { 1, 1, 1, 1, 1 }, in board_heartbeat()
152 { 1, 1, 1, 1, 1 }), in board_heartbeat()
153 MB_IMAGE({ 1, 1, 1, 1, 1 }, in board_heartbeat()
154 { 1, 1, 1, 1, 1 }, in board_heartbeat()
155 { 1, 1, 0, 1, 1 }, in board_heartbeat()
[all …]
|
| /Zephyr-Core-2.7.6/samples/boards/bbc_microbit/display/src/ |
| D | main.c | 14 static struct mb_image smiley = MB_IMAGE({ 0, 1, 0, 1, 0 },
15 { 0, 1, 0, 1, 0 },
17 { 1, 0, 0, 0, 1 },
18 { 0, 1, 1, 1, 0 });
21 MB_IMAGE({ 1, 0, 0, 0, 0 },
22 { 1, 0, 0, 0, 1 },
23 { 1, 0, 0, 1, 0 },
24 { 1, 0, 1, 0, 0 },
25 { 1, 1, 0, 0, 0 }),
26 MB_IMAGE({ 1, 0, 0, 0, 0 },
[all …]
|
| /Zephyr-Core-2.7.6/modules/hal_nordic/nrfx/ |
| D | nrfx_config.h | 19 #define NRFX_ADC_ENABLED 1
23 #define NRFX_CLOCK_ENABLED 1
28 #define NRFX_CLOCK_CONFIG_LF_SRC 1
38 #define NRFX_CLOCK_CONFIG_LF_SRC 1
59 #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 1
63 #define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 1
67 #define NRFX_COMP_ENABLED 1
71 #define NRFX_DPPI_ENABLED 1
75 #define NRFX_EGU_ENABLED 1
78 #define NRFX_EGU0_ENABLED 1
[all …]
|
| /Zephyr-Core-2.7.6/samples/bluetooth/mesh/src/ |
| D | microbit.c | 24 MB_IMAGE({ 1, 1, 1, 1, 1 },
25 { 1, 1, 1, 1, 1 },
26 { 1, 1, 1, 1, 1 },
27 { 1, 1, 1, 1, 1 },
28 { 1, 1, 1, 1, 1 }),
64 const struct mb_image arrow = MB_IMAGE({ 0, 0, 1, 0, 0 }, in board_output_number()
65 { 0, 1, 0, 0, 0 }, in board_output_number()
66 { 1, 1, 1, 1, 1 }, in board_output_number()
67 { 0, 1, 0, 0, 0 }, in board_output_number()
68 { 0, 0, 1, 0, 0 }); in board_output_number()
[all …]
|
| /Zephyr-Core-2.7.6/tests/bluetooth/mesh/src/ |
| D | microbit.c | 50 struct mb_image arrow = MB_IMAGE({ 0, 0, 1, 0, 0 }, in board_output_number()
51 { 0, 1, 0, 0, 0 }, in board_output_number()
52 { 1, 1, 1, 1, 1 }, in board_output_number()
53 { 0, 1, 0, 0, 0 }, in board_output_number()
54 { 0, 0, 1, 0, 0 }); in board_output_number()
62 1); in board_output_number()
68 struct mb_image arrow = MB_IMAGE({ 0, 1, 0, 1, 0 }, in board_prov_complete()
69 { 0, 1, 0, 1, 0 }, in board_prov_complete()
71 { 1, 0, 0, 0, 1 }, in board_prov_complete()
72 { 0, 1, 1, 1, 0 }); in board_prov_complete()
[all …]
|
| /Zephyr-Core-2.7.6/soc/nios2/nios2f-zephyr/cpu/ |
| D | ghrd_10m50da.qsys | 101 value = "1";
162 value = "1";
175 value = "1";
183 value = "1";
196 value = "1";
217 value = "1";
292 <parameter name="maxAdditionalLatency" value="1" />
336 enabled="1">
341 <parameter name="FIFO_MODE" value="1" />
346 …1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED…
[all …]
|
| /Zephyr-Core-2.7.6/drivers/i2s/ |
| D | i2s_cavs.h | 43 #define SSCR0_DSIZE(x) ((x) - 1)
46 #define SSCR0_TI (1 << 4)
49 #define SSCR0_ECS (1 << 6)
50 #define SSCR0_SSE (1 << 7)
53 #define SSCR0_EDSS (1 << 20)
54 #define SSCR0_NCS (1 << 21)
55 #define SSCR0_RIM (1 << 22)
56 #define SSCR0_TIM (1 << 23)
57 #define SSCR0_FRDC(x) (((x) - 1) << 24)
58 #define SSCR0_ACS (1 << 30)
[all …]
|
| /Zephyr-Core-2.7.6/boards/arc/nsim/support/ |
| D | nsim_em.props | 13 nsim_isa_div_rem_option=1
14 nsim_isa_turbo_boost=1
15 nsim_isa_swap_option=1
16 nsim_isa_bitscan_option=1
22 nsim_isa_dsp_complex_option=1
23 nsim_isa_dsp_divsqrt_option=1
24 nsim_isa_dsp_itu_option=1
25 nsim_isa_dsp_itu_option=1
29 nsim_isa_agu_accord=1
30 nsim_isa_xy=1
[all …]
|
| D | nsim_sem_mpu_stack_guard.props | 4 nsim_isa_rgf_num_banks=1
6 nsim_isa_rgf_num_wr_ports=1
12 nsim_isa_div_rem_option=1
13 nsim_isa_turbo_boost=1
14 nsim_isa_swap_option=1
15 nsim_isa_bitscan_option=1
19 nsim_isa_dsp_complex_option=1
20 nsim_isa_dsp_divsqrt_option=1
21 nsim_isa_dsp_accshift_option=1
22 nsim_isa_enable_timer_0=1
[all …]
|
| D | nsim_sem.props | 4 nsim_isa_rgf_num_banks=1
6 nsim_isa_rgf_num_wr_ports=1
12 nsim_isa_div_rem_option=1
13 nsim_isa_turbo_boost=1
14 nsim_isa_swap_option=1
15 nsim_isa_bitscan_option=1
19 nsim_isa_dsp_complex_option=1
20 nsim_isa_dsp_divsqrt_option=1
21 nsim_isa_dsp_accshift_option=1
22 nsim_isa_enable_timer_0=1
[all …]
|
| D | nsim_em7d_v22.props | 4 nsim_isa_rgf_num_banks=1
6 nsim_isa_rgf_num_wr_ports=1
12 nsim_isa_div_rem_option=1
13 nsim_isa_turbo_boost=1
14 nsim_isa_swap_option=1
15 nsim_isa_bitscan_option=1
19 nsim_isa_dsp_complex_option=1
20 nsim_isa_dsp_divsqrt_option=1
21 nsim_isa_dsp_accshift_option=1
22 nsim_isa_enable_timer_0=1
[all …]
|
| /Zephyr-Core-2.7.6/drivers/clock_control/ |
| D | Kconfig.stm32h7 | 13 default 1
14 range 1 8
17 allowed values: 1, 2, 4, 8
23 default 1
24 range 1 512
27 allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.
31 default 1
32 range 1 512
34 hclk prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.
38 default 1
[all …]
|
| /Zephyr-Core-2.7.6/soc/arm/atmel_sam0/common/ |
| D | tc_fixup_samd5x.h | 9 #define MCLK_TC0_MASK ((1 << MCLK_APBAMASK_TC0_Pos) | (1 << MCLK_APBAMASK_TC1_Pos))
13 #define MCLK_TC0_MASK ((1 << MCLK_APBBMASK_TC0_Pos) | (1 << MCLK_APBBMASK_TC1_Pos))
17 #define MCLK_TC0_MASK ((1 << MCLK_APBCMASK_TC0_Pos) | (1 << MCLK_APBCMASK_TC1_Pos))
21 #define MCLK_TC0_MASK ((1 << MCLK_APBDMASK_TC0_Pos) | (1 << MCLK_APBDMASK_TC1_Pos))
26 #define MCLK_TC2_MASK ((1 << MCLK_APBAMASK_TC2_Pos) | (1 << MCLK_APBAMASK_TC3_Pos))
30 #define MCLK_TC2_MASK ((1 << MCLK_APBBMASK_TC2_Pos) | (1 << MCLK_APBBMASK_TC3_Pos))
34 #define MCLK_TC2_MASK ((1 << MCLK_APBCMASK_TC2_Pos) | (1 << MCLK_APBCMASK_TC3_Pos))
38 #define MCLK_TC2_MASK ((1 << MCLK_APBDMASK_TC2_Pos) | (1 << MCLK_APBDMASK_TC3_Pos))
43 #define MCLK_TC4_MASK ((1 << MCLK_APBAMASK_TC4_Pos) | (1 << MCLK_APBAMASK_TC5_Pos))
47 #define MCLK_TC4_MASK ((1 << MCLK_APBBMASK_TC4_Pos) | (1 << MCLK_APBBMASK_TC5_Pos))
[all …]
|
| /Zephyr-Core-2.7.6/drivers/i2c/ |
| D | i2c_dw_registers.h | 19 uint32_t master_mode : 1 __packed;
21 uint32_t addr_slave_10bit : 1 __packed;
22 uint32_t addr_master_10bit : 1 __packed;
23 uint32_t restart_en : 1 __packed;
24 uint32_t slave_disable : 1 __packed;
25 uint32_t stop_det : 1 __packed;
26 uint32_t tx_empty_ctl : 1 __packed;
27 uint32_t rx_fifo_full : 1 __packed;
33 #define IC_DATA_CMD_CMD (1 << 8)
34 #define IC_DATA_CMD_STOP (1 << 9)
[all …]
|
| /Zephyr-Core-2.7.6/tests/net/socket/socketpair/src/ |
| D | test_socketpair_poll.c | 46 struct pollfd fds[1]; in test_socketpair_poll_timeout_common()
51 res = poll(fds, 1, 1); in test_socketpair_poll_timeout_common()
55 res = write(sv[0], "x", 1); in test_socketpair_poll_timeout_common()
56 zassert_equal(res, 1, "write failed: %d", res); in test_socketpair_poll_timeout_common()
62 res = poll(fds, 1, 1); in test_socketpair_poll_timeout_common()
66 close(sv[1]); in test_socketpair_poll_timeout_common()
71 int sv[2] = {-1, -1}; in test_socketpair_poll_timeout()
74 zassert_not_equal(res, -1, "socketpair failed: %d", errno); in test_socketpair_poll_timeout()
82 int sv[2] = {-1, -1}; in test_socketpair_poll_timeout_nonblocking()
85 zassert_not_equal(res, -1, "socketpair failed: %d", errno); in test_socketpair_poll_timeout_nonblocking()
[all …]
|
| /Zephyr-Core-2.7.6/soc/arm/microchip_mec/mec172x/reg/ |
| D | mec172x_defs.h | 18 * Delay register address. Write n to delay for n + 1 microseconds where
28 #define MCHP_ACMP_INSTANCES 1
30 #define MCHP_ACPI_PM1_INSTANCES 1
31 #define MCHP_ADC_INSTANCES 1
32 #define MCHP_BCL_INSTANCES 1
35 #define MCHP_CCT_INSTANCES 1
37 #define MCHP_DMA_INSTANCES 1
38 #define MCHP_ECIA_INSTANCES 1
44 #define MCHP_MBOX_INSTANCES 1
45 #define MCHP_OTP_INSTANCES 1
[all …]
|
| /Zephyr-Core-2.7.6/dts/riscv/ |
| D | riscv32-fe310.dtsi | 6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
28 #interrupt-cells = <1>;
35 #address-cells = <1>;
36 #size-cells = <1>;
43 interrupts = <1 1>;
51 interrupts = <2 1>;
56 #interrupt-cells = <1>;
83 interrupts = <8 1>, <9 1>, <10 1>, <11 1>,
[all …]
|
| /Zephyr-Core-2.7.6/drivers/ethernet/ |
| D | phy_xlnx_gem.h | 17 #define PHY_XLNX_GEM_EVENT_LINK_SPEED_CHANGED (1 << 0)
18 #define PHY_XLNX_GEM_EVENT_LINK_STATE_CHANGED (1 << 1)
19 #define PHY_XLNX_GEM_EVENT_AUTONEG_COMPLETE (1 << 2)
34 #define PHY_MRVL_COPPER_STATUS_REGISTER 1
46 #define PHY_MRVL_GENERAL_CONTROL_1_RESET_BIT (1 << 15)
48 #define PHY_MRVL_COPPER_CONTROL_RESET_BIT (1 << 15)
49 #define PHY_MRVL_COPPER_CONTROL_AUTONEG_ENABLE_BIT (1 << 12)
51 #define PHY_MRVL_ADV_1000BASET_FDX_BIT (1 << 9)
52 #define PHY_MRVL_ADV_1000BASET_HDX_BIT (1 << 8)
53 #define PHY_MRVL_ADV_100BASET_FDX_BIT (1 << 8)
[all …]
|
| /Zephyr-Core-2.7.6/scripts/ |
| D | tags.sh | 13 find "$1" -name "$2"
57 all_target_sources | xargs $1 -a \
72 --regex-c='/^SYSCALL_DEFINE[[:digit:]]?\(([^,)]*).*/sys_\1/' \
73 --regex-c='/^COMPAT_SYSCALL_DEFINE[[:digit:]]?\(([^,)]*).*/compat_sys_\1/' \
74 --regex-c++='/^TRACE_EVENT\(([^,)]*).*/trace_\1/' \
75 --regex-c++='/^TRACE_EVENT\(([^,)]*).*/trace_\1_rcuidle/' \
76 --regex-c++='/^DEFINE_EVENT\([^,)]*, *([^,)]*).*/trace_\1/' \
77 --regex-c++='/^DEFINE_EVENT\([^,)]*, *([^,)]*).*/trace_\1_rcuidle/' \
78 --regex-c++='/PAGEFLAG\(([^,)]*).*/Page\1/' \
79 --regex-c++='/PAGEFLAG\(([^,)]*).*/SetPage\1/' \
[all …]
|
| /Zephyr-Core-2.7.6/drivers/sensor/ens210/ |
| D | ens210.h | 33 #define ENS210_T_START 1
35 #define ENS210_T_RUN 1
36 #define ENS210_T_START 1
44 #define ENS210_H_START 1
46 #define ENS210_H_RUN 1
47 #define ENS210_H_START 1
57 #define ENS210_CRC7_IVEC ((1UL << ENS210_CRC7_WIDTH) - 1)
59 #define ENS210_CRC7_DATA_MASK ((1UL << ENS210_CRC7_DATA_WIDTH) - 1)
60 #define ENS210_CRC7_DATA_MSB (1UL << (ENS210_CRC7_DATA_WIDTH - 1))
64 uint8_t valid : 1;
[all …]
|
| /Zephyr-Core-2.7.6/scripts/dts/python-devicetree/tests/ |
| D | test.dts | 23 interrupts = <1 2 3 4 5 6>;
31 #interrupt-cells = <1>;
34 controller-1 {
46 &{/interrupts-extended-test/controller-0} 1
47 &{/interrupts-extended-test/controller-1} 2 3
57 #address-cells = <1>;
58 #interrupt-cells = <1>;
61 controller-1 {
77 0 0 0 1 &{/interrupt-map-test/controller-1} 0 0 0 1
79 0 1 0 0 &{/interrupt-map-test/controller-0} 0 3
[all …]
|
| /Zephyr-Core-2.7.6/include/net/ |
| D | mii.h | 26 /** PHY ID 1 Register */
49 #define MII_BMCR_RESET (1 << 15)
51 #define MII_BMCR_LOOPBACK (1 << 14)
53 #define MII_BMCR_SPEED_LSB (1 << 13)
55 #define MII_BMCR_AUTONEG_ENABLE (1 << 12)
57 #define MII_BMCR_POWER_DOWN (1 << 11)
59 #define MII_BMCR_ISOLATE (1 << 10)
61 #define MII_BMCR_AUTONEG_RESTART (1 << 9)
63 #define MII_BMCR_DUPLEX_MODE (1 << 8)
65 #define MII_BMCR_SPEED_MSB (1 << 6)
[all …]
|
| /Zephyr-Core-2.7.6/soc/xtensa/sample_controller/include/ |
| D | _soc_inthandlers.h | 16 #if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
19 #if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
22 #if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1
25 #if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1
28 #if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1
31 #if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1
34 #if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
37 #if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1
40 #if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 1
43 #if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 1
[all …]
|
| /Zephyr-Core-2.7.6/drivers/sensor/adxl362/ |
| D | adxl362.h | 15 #define ADXL362_SLAVE_ID 1
59 #define ADXL362_STATUS_ERR_USER_REGS (1 << 7)
60 #define ADXL362_STATUS_AWAKE (1 << 6)
61 #define ADXL362_STATUS_INACT (1 << 5)
62 #define ADXL362_STATUS_ACT (1 << 4)
63 #define ADXL362_STATUS_FIFO_OVERRUN (1 << 3)
64 #define ADXL362_STATUS_FIFO_WATERMARK (1 << 2)
65 #define ADXL362_STATUS_FIFO_RDY (1 << 1)
66 #define ADXL362_STATUS_DATA_RDY (1 << 0)
70 #define ADXL362_ACT_INACT_CTL_INACT_REF (1 << 3)
[all …]
|
