1/* SPDX-License-Identifier: Apache-2.0 */ 2 3#include <dt-bindings/gpio/gpio.h> 4 5/ { 6 #address-cells = <1>; 7 #size-cells = <1>; 8 compatible = "sifive,FE310G-0002-Z0-dev", "fe310-dev", "sifive-dev"; 9 model = "SiFive,FE310G-0002-Z0"; 10 cpus { 11 #address-cells = <1>; 12 #size-cells = <0>; 13 cpu: cpu@0 { 14 clock-frequency = <0>; 15 compatible = "sifive,rocket0", "riscv"; 16 device_type = "cpu"; 17 i-cache-block-size = <64>; 18 i-cache-sets = <128>; 19 i-cache-size = <16384>; 20 next-level-cache = <&modeselect &maskrom &otp &spi0>; 21 reg = <0>; 22 riscv,isa = "rv32imac"; 23 sifive,dtim = <&dtim>; 24 sifive,itim = <&itim>; 25 status = "okay"; 26 timebase-frequency = <32768>; 27 hlic: interrupt-controller { 28 #interrupt-cells = <1>; 29 compatible = "riscv,cpu-intc"; 30 interrupt-controller; 31 }; 32 }; 33 }; 34 soc { 35 #address-cells = <1>; 36 #size-cells = <1>; 37 compatible = "sifive,FE310G-0002-Z0-soc", "fe310-soc", 38 "sifive-soc", "simple-bus"; 39 ranges; 40 wdog0: wdog@10000000 { 41 compatible = "sifive,wdt"; 42 interrupt-parent = <&plic>; 43 interrupts = <1 1>; 44 reg = <0x10000000 0x40>; 45 reg-names = "control"; 46 label = "WDOG0"; 47 }; 48 aon: aon@10000040 { 49 compatible = "sifive,aon0"; 50 interrupt-parent = <&plic>; 51 interrupts = <2 1>; 52 reg = <0x10000040 0x9c0>; 53 reg-names = "control"; 54 }; 55 clint: clint@2000000 { 56 #interrupt-cells = <1>; 57 compatible = "riscv,clint0"; 58 interrupt-controller; 59 interrupts-extended = <&hlic 3 &hlic 7>; 60 reg = <0x2000000 0x10000>; 61 reg-names = "control"; 62 }; 63 debug: debug-controller@0 { 64 compatible = "sifive,debug-013", "riscv,debug-013"; 65 interrupts-extended = <&hlic 65535>; 66 reg = <0x0 0x1000>; 67 reg-names = "control"; 68 }; 69 dtim: dtim@80000000 { 70 compatible = "sifive,dtim0"; 71 reg = <0x80000000 0x4000>; 72 reg-names = "mem"; 73 }; 74 error-device@3000 { 75 compatible = "sifive,error0"; 76 reg = <0x3000 0x1000>; 77 reg-names = "mem"; 78 }; 79 gpio0: gpio@10012000 { 80 compatible = "sifive,gpio0"; 81 gpio-controller; 82 interrupt-parent = <&plic>; 83 interrupts = <8 1>, <9 1>, <10 1>, <11 1>, 84 <12 1>, <13 1>, <14 1>, <15 1>, 85 <16 1>, <17 1>, <18 1>, <19 1>, 86 <20 1>, <21 1>, <22 1>, <23 1>, 87 <24 1>, <25 1>, <26 1>, <27 1>, 88 <28 1>, <29 1>, <30 1>, <31 1>, 89 <32 1>, <33 1>, <34 1>, <35 1>, 90 <36 1>, <37 1>, <38 1>, <39 1>; 91 reg = <0x10012000 0x1000>; 92 reg-names = "control"; 93 label = "gpio_0"; 94 status = "disabled"; 95 #gpio-cells = <2>; 96 97 #address-cells = <1>; 98 #size-cells = <1>; 99 ranges; 100 101 pinctrl: pinctrl@10012038 { 102 compatible = "sifive,iof"; 103 reg = <0x10012038 0x8>; 104 }; 105 }; 106 i2c0: i2c@10016000 { 107 compatible = "sifive,i2c0"; 108 interrupt-parent = <&plic>; 109 interrupts = <52 1>; 110 reg = <0x10016000 0x1000>; 111 reg-names = "control"; 112 label = "i2c_0"; 113 status = "disabled"; 114 #address-cells = <1>; 115 #size-cells = <0>; 116 }; 117 plic: interrupt-controller@c000000 { 118 #interrupt-cells = <2>; 119 compatible = "sifive,plic-1.0.0"; 120 interrupt-controller; 121 interrupts-extended = <&hlic 11>; 122 reg = <0x0c000000 0x00002000 123 0x0c002000 0x001fe000 124 0x0c200000 0x03e00000>; 125 reg-names = "prio", "irq_en", "reg"; 126 riscv,max-priority = <7>; 127 riscv,ndev = <52>; 128 }; 129 itim: itim@8000000 { 130 compatible = "sifive,itim0"; 131 reg = <0x8000000 0x4000>; 132 reg-names = "mem"; 133 }; 134 otp: otp@10010000 { 135 compatible = "sifive,otp0"; 136 reg = <0x10010000 0x1000 0x20000 0x2000>; 137 reg-names = "control", "mem"; 138 }; 139 prci: prci@10008000 { 140 compatible = "sifive,freedome300prci0"; 141 reg = <0x10008000 0x1000>; 142 reg-names = "control"; 143 }; 144 pwm0: pwm@10015000 { 145 compatible = "sifive,pwm0"; 146 interrupt-parent = <&plic>; 147 interrupts = <40 1>, <41 1>, <42 1>, <43 1>; 148 reg = <0x10015000 0x1000>; 149 reg-names = "control"; 150 label = "pwm_0"; 151 status = "disabled"; 152 sifive,compare-width = <8>; 153 #pwm-cells = <2>; 154 }; 155 pwm1: pwm@10025000 { 156 compatible = "sifive,pwm0"; 157 interrupt-parent = <&plic>; 158 interrupts = <44 1>, <45 1>, <46 1>, <47 1>; 159 reg = <0x10025000 0x1000>; 160 reg-names = "control"; 161 label = "pwm_1"; 162 status = "disabled"; 163 sifive,compare-width = <16>; 164 #pwm-cells = <2>; 165 }; 166 pwm2: pwm@10035000 { 167 compatible = "sifive,pwm0"; 168 interrupt-parent = <&plic>; 169 interrupts = <48 1>, <49 1>, <50 1>, <51 1>; 170 reg = <0x10035000 0x1000>; 171 reg-names = "control"; 172 label = "pwm_2"; 173 status = "disabled"; 174 sifive,compare-width = <16>; 175 #pwm-cells = <2>; 176 }; 177 modeselect: rom@1000 { 178 compatible = "sifive,modeselect0"; 179 reg = <0x1000 0x1000>; 180 reg-names = "mem"; 181 }; 182 maskrom: rom@10000 { 183 compatible = "sifive,maskrom0"; 184 reg = <0x10000 0x2000>; 185 reg-names = "mem"; 186 }; 187 uart0: serial@10013000 { 188 compatible = "sifive,uart0"; 189 interrupt-parent = <&plic>; 190 interrupts = <3 1>; 191 reg = <0x10013000 0x1000>; 192 reg-names = "control"; 193 label = "uart_0"; 194 status = "disabled"; 195 }; 196 uart1: serial@10023000 { 197 compatible = "sifive,uart0"; 198 interrupt-parent = <&plic>; 199 interrupts = <4 1>; 200 reg = <0x10023000 0x1000>; 201 reg-names = "control"; 202 label = "uart_1"; 203 status = "disabled"; 204 }; 205 spi0: spi@10014000 { 206 compatible = "sifive,spi0"; 207 interrupt-parent = <&plic>; 208 interrupts = <5 1>; 209 reg = <0x10014000 0x1000 0x20000000 0x20000000>; 210 reg-names = "control", "mem"; 211 label = "spi_0"; 212 status = "disabled"; 213 #address-cells = <1>; 214 #size-cells = <0>; 215 }; 216 spi1: spi@10024000 { 217 compatible = "sifive,spi0"; 218 interrupt-parent = <&plic>; 219 interrupts = <6 1>; 220 reg = <0x10024000 0x1000>; 221 reg-names = "control"; 222 label = "spi_1"; 223 status = "disabled"; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 }; 227 spi2: spi@10034000 { 228 compatible = "sifive,spi0"; 229 interrupt-parent = <&plic>; 230 interrupts = <7 1>; 231 reg = <0x10034000 0x1000>; 232 reg-names = "control"; 233 label = "spi_2"; 234 status = "disabled"; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 }; 238 teststatus: teststatus@4000 { 239 compatible = "sifive,test0"; 240 reg = <0x4000 0x1000>; 241 reg-names = "control"; 242 }; 243 }; 244}; 245
