1# STM32H7 PLL configuration options
2
3# Copyright (c) 2019 Linaro
4# SPDX-License-Identifier: Apache-2.0
5
6if SOC_SERIES_STM32H7X
7
8# Oscillator clocks configuration options
9
10config CLOCK_STM32_HSI_DIVISOR
11	int "HSI Divisor"
12	depends on CLOCK_STM32_PLL_SRC_HSI || CLOCK_STM32_SYSCLK_SRC_HSI
13	default 1
14	range 1 8
15	help
16	  HSI Divisor to divide HSI base frequency value
17	  allowed values: 1, 2, 4, 8
18
19# Bus clocks configuration options
20
21config CLOCK_STM32_D1CPRE
22	int "D1 Domain, CPU1 clock prescaler"
23	default 1
24	range 1 512
25	help
26	  D1 Domain, CPU1 clock (sys_d1cpre_ck prescaler),
27	  allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.
28
29config CLOCK_STM32_HPRE
30	int "hclk prescaler, D2 domain (CPU2) Clock prescaler"
31	default 1
32	range 1 512
33	help
34	  hclk prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.
35
36config CLOCK_STM32_D2PPRE1
37	int "APB1 prescaler"
38	default 1
39	range 1 16
40	help
41	  APB1 clock (rcc_pclk1) prescaler, allowed values: 1, 2, 4, 8, 16
42
43config CLOCK_STM32_D2PPRE2
44	int "D2 DOMAIN, APB2 prescaler"
45	default 1
46	range 1 16
47	help
48	  APB2 clock (rcc_pclk2) prescaler, allowed values: 1, 2, 4, 8, 16
49
50config CLOCK_STM32_D1PPRE
51	int "D1 DOMAIN, APB3 prescaler"
52	default 1
53	range 1 16
54	help
55	  APB3 clock (rcc_pclk3) prescaler, allowed values: 1, 2, 4, 8, 16
56
57config CLOCK_STM32_D3PPRE
58	int "APB4 prescaler"
59	default 1
60	range 1 16
61	help
62	  APB4 clock (rcc_pclk4) prescaler, allowed values: 1, 2, 4, 8, 16
63
64
65# PLL settings
66
67config CLOCK_STM32_PLL_M_DIVISOR
68	int "PLL divisor"
69	depends on CLOCK_STM32_SYSCLK_SRC_PLL
70	default 32
71	range 0 63
72	help
73	  PLL divisor, allowed values: 0-63.
74
75config CLOCK_STM32_PLL_N_MULTIPLIER
76	int "PLL1 VCO multiplier"
77	depends on CLOCK_STM32_SYSCLK_SRC_PLL
78	default 129
79	range 4 512
80	help
81	  PLL multiplier, allowed values: 4-512.
82
83config CLOCK_STM32_PLL_P_DIVISOR
84	int "PLL P Divisor"
85	depends on CLOCK_STM32_SYSCLK_SRC_PLL
86	default 2
87	range 1 128
88	help
89	  PLL P Output divisor, allowed values: 1-128.
90
91config CLOCK_STM32_PLL_Q_DIVISOR
92	int "PLL Q Divisor"
93	depends on CLOCK_STM32_SYSCLK_SRC_PLL
94	default 2
95	range 1 128
96	help
97	  PLL Q Output divisor, allowed values: 1-128.
98
99config CLOCK_STM32_PLL_R_DIVISOR
100	int "PLL R Divisor"
101	depends on CLOCK_STM32_SYSCLK_SRC_PLL
102	default 2
103	range 1 128
104	help
105	  PLL R Output divisor, allowed values: 1-128.
106
107# PLL3 settings
108
109config CLOCK_STM32_PLL3_ENABLE
110	bool "Enable PLL3"
111	help
112	  Enable PLL3. It is used to generate the kernel clock for some peripherals.
113
114if CLOCK_STM32_PLL3_ENABLE
115
116config CLOCK_STM32_PLL3_M_DIVISOR
117	int "PLL3 divisor"
118	default 32
119	range 1 63
120	help
121	  PLL divisor, allowed values: 1-63.
122
123config CLOCK_STM32_PLL3_N_MULTIPLIER
124	int "PLL3 VCO multiplier"
125	default 129
126	range 4 512
127	help
128	  PLL3 multiplier, allowed values: 4-512.
129
130config CLOCK_STM32_PLL3_P_ENABLE
131	bool "Enable PLL3 P output"
132	help
133	  Enable PLL3 P output.
134
135config CLOCK_STM32_PLL3_P_DIVISOR
136	int "PLL3 P Divisor"
137	depends on CLOCK_STM32_PLL3_P_ENABLE
138	default 2
139	range 1 128
140	help
141	  PLL3 P Output divisor, allowed values: 1-128.
142
143config CLOCK_STM32_PLL3_Q_ENABLE
144	bool "Enable PLL3 Q output"
145	help
146	  Enable PLL3 Q output.
147
148config CLOCK_STM32_PLL3_Q_DIVISOR
149	int "PLL3 Q Divisor"
150	depends on CLOCK_STM32_PLL3_Q_ENABLE
151	default 2
152	range 1 128
153	help
154	  PLL3 Q Output divisor, allowed values: 1-128.
155
156config CLOCK_STM32_PLL3_R_ENABLE
157	bool "Enable PLL3 R output"
158	help
159	  Enable PLL3 R output.
160
161config CLOCK_STM32_PLL3_R_DIVISOR
162	int "PLL3 R Divisor"
163	depends on CLOCK_STM32_PLL3_R_ENABLE
164	default 2
165	range 1 128
166	help
167	  PLL3 R Output divisor, allowed values: 1-128.
168
169endif # CLOCK_STM32_PLL3_ENABLE
170
171endif # SOC_SERIES_STM32H7X
172