1 /* 2 * Copyright (c) 2018 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** @file 8 * @brief I2S bus (SSP) driver for Intel CAVS. 9 * 10 * Limitations: 11 * - DMA is used in simple single block transfer mode (with linked list 12 * enabled) and "interrupt on full transfer completion" mode. 13 */ 14 15 #ifndef ZEPHYR_DRIVERS_I2S_I2S_CAVS_H_ 16 #define ZEPHYR_DRIVERS_I2S_I2S_CAVS_H_ 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 struct i2s_cavs_ssp { 23 uint32_t ssc0; /* 0x00 - Control0 */ 24 uint32_t ssc1; /* 0x04 - Control1 */ 25 uint32_t sss; /* 0x08 - Status */ 26 uint32_t ssit; /* 0x0C - Interrupt Test */ 27 uint32_t ssd; /* 0x10 - Data */ 28 uint32_t reserved0[5]; 29 uint32_t ssto; /* 0x28 - Time Out */ 30 uint32_t sspsp; /* 0x2C - Programmable Serial Protocol */ 31 uint32_t sstsa; /* 0x30 - TX Time Slot Active */ 32 uint32_t ssrsa; /* 0x34 - RX Time Slot Active */ 33 uint32_t sstss; /* 0x38 - Time Slot Status */ 34 uint32_t reserved1; 35 uint32_t ssc2; /* 0x40 - Command / Status 2 */ 36 uint32_t sspsp2; /* 0x44 - Programmable Serial Protocol 2 */ 37 uint32_t ssc3; /* 0x48 - Command / Status 3 */ 38 uint32_t ssioc; /* 0x4C - IO Control */ 39 }; 40 41 /* SSCR0 bits */ 42 #define SSCR0_DSS_MASK (0x0000000f) 43 #define SSCR0_DSIZE(x) ((x) - 1) 44 #define SSCR0_FRF (0x00000030) 45 #define SSCR0_MOT (00 << 4) 46 #define SSCR0_TI (1 << 4) 47 #define SSCR0_NAT (2 << 4) 48 #define SSCR0_PSP (3 << 4) 49 #define SSCR0_ECS (1 << 6) 50 #define SSCR0_SSE (1 << 7) 51 #define SSCR0_SCR_MASK (0x000fff00) 52 #define SSCR0_SCR(x) ((x) << 8) 53 #define SSCR0_EDSS (1 << 20) 54 #define SSCR0_NCS (1 << 21) 55 #define SSCR0_RIM (1 << 22) 56 #define SSCR0_TIM (1 << 23) 57 #define SSCR0_FRDC(x) (((x) - 1) << 24) 58 #define SSCR0_ACS (1 << 30) 59 #define SSCR0_MOD (1 << 31) 60 61 /* SSCR1 bits */ 62 #define SSCR1_RIE (1 << 0) 63 #define SSCR1_TIE (1 << 1) 64 #define SSCR1_LBM (1 << 2) 65 #define SSCR1_SPO (1 << 3) 66 #define SSCR1_SPH (1 << 4) 67 #define SSCR1_MWDS (1 << 5) 68 #define SSCR1_EFWR (1 << 14) 69 #define SSCR1_STRF (1 << 15) 70 #define SSCR1_IFS (1 << 16) 71 #define SSCR1_PINTE (1 << 18) 72 #define SSCR1_TINTE (1 << 19) 73 #define SSCR1_RSRE (1 << 20) 74 #define SSCR1_TSRE (1 << 21) 75 #define SSCR1_TRAIL (1 << 22) 76 #define SSCR1_RWOT (1 << 23) 77 #define SSCR1_SFRMDIR (1 << 24) 78 #define SSCR1_SCLKDIR (1 << 25) 79 #define SSCR1_ECRB (1 << 26) 80 #define SSCR1_ECRA (1 << 27) 81 #define SSCR1_SCFR (1 << 28) 82 #define SSCR1_EBCEI (1 << 29) 83 #define SSCR1_TTE (1 << 30) 84 #define SSCR1_TTELP (1 << 31) 85 86 /* SSCR2 bits */ 87 #define SSCR2_TURM1 (1 << 1) 88 #define SSCR2_SDFD (1 << 14) 89 #define SSCR2_SDPM (1 << 16) 90 #define SSCR2_LJDFD (1 << 17) 91 92 /* SSR bits */ 93 #define SSSR_TNF (1 << 2) 94 #define SSSR_RNE (1 << 3) 95 #define SSSR_BSY (1 << 4) 96 #define SSSR_TFS (1 << 5) 97 #define SSSR_RFS (1 << 6) 98 #define SSSR_ROR (1 << 7) 99 #define SSSR_TUR (1 << 21) 100 101 /* SSPSP bits */ 102 #define SSPSP_SCMODE(x) ((x) << 0) 103 #define SSPSP_SFRMP(x) ((x) << 2) 104 #define SSPSP_ETDS (1 << 3) 105 #define SSPSP_STRTDLY(x) ((x) << 4) 106 #define SSPSP_DMYSTRT(x) ((x) << 7) 107 #define SSPSP_SFRMDLY(x) ((x) << 9) 108 #define SSPSP_SFRMWDTH(x) ((x) << 16) 109 #define SSPSP_DMYSTOP(x) ((x) << 23) 110 #define SSPSP_FSRT (1 << 25) 111 #define SSPSP_EDMYSTOP(x) ((x) << 26) 112 113 /* SSTSA bits */ 114 #define SSTSA_TTSA(x) (1 << x) 115 #define SSTSA_TXEN (1 << 8) 116 117 /* SSRSA bits */ 118 #define SSRSA_RTSA(x) (1 << x) 119 #define SSRSA_RXEN (1 << 8) 120 121 /* SSCR3 bits */ 122 #define SSCR3_TFL_MASK (0x0000003f) 123 #define SSCR3_RFL_MASK (0x00003f00) 124 #define SSCR3_TFT_MASK (0x003f0000) 125 #define SSCR3_TX(x) (((x) - 1) << 16) 126 #define SSCR3_RFT_MASK (0x3f000000) 127 #define SSCR3_RX(x) (((x) - 1) << 24) 128 129 /* SSIOC bits */ 130 #define SSIOC_TXDPDEB (1 << 1) 131 #define SSIOC_SFCR (1 << 4) 132 #define SSIOC_SCOE (1 << 5) 133 134 struct i2s_cavs_mn_div { 135 uint32_t mval; /* 0x00 - M value */ 136 uint32_t nval; /* 0x04 - N value */ 137 }; 138 139 /* MVAL & NVAL bits */ 140 #define I2S_MNVAL_MASK (BIT_MASK(24)) 141 #define I2S_MNVAL(x) ((x) & I2S_MNVAL_MASK) 142 143 #ifdef __cplusplus 144 } 145 #endif 146 147 #endif /* ZEPHYR_DRIVERS_I2S_I2S_CAVS_H_ */ 148
