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Searched +full:0 +full:xfffffff0 (Results 1 – 13 of 13) sorted by relevance

/Zephyr-latest/tests/drivers/gpio/gpio_reserved_ranges/src/
Dmain.c46 0xdeadbeef, ""); in ZTEST()
48 0x7fffbeff, ""); in ZTEST()
50 0xfffc0418, ""); in ZTEST()
52 0xfffffff0, ""); in ZTEST()
53 zassert_equal(GPIO_DT_RESERVED_RANGES_NGPIOS(TEST_GPIO_5, 0), in ZTEST()
54 0xffffffff, ""); in ZTEST()
56 0, ""); in ZTEST()
59 zassert_equal(GPIO_DT_INST_RESERVED_RANGES_NGPIOS(0, 32), 0xdeadbeef, in ZTEST()
61 zassert_equal(GPIO_DT_INST_RESERVED_RANGES_NGPIOS(1, 32), 0x7fffbeff, in ZTEST()
63 zassert_equal(GPIO_DT_INST_RESERVED_RANGES_NGPIOS(2, 18), 0xfffc0418, in ZTEST()
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/Zephyr-latest/dts/bindings/mbox/
Dnordic,nrf-vevif-task-tx.yaml18 cpuppr_vevif_task_tx: mailbox@0 {
20 reg = <0x0 0x1000>;
23 nordic,tasks-mask = <0xfffffff0>;
Dnordic,nrf-vevif-task-rx.yaml20 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>,
26 nordic,tasks-mask = <0xfffffff0>;
/Zephyr-latest/drivers/ethernet/
Dphy_xlnx_gem.h17 #define PHY_XLNX_GEM_EVENT_LINK_SPEED_CHANGED (1 << 0)
27 /* Marvell PHY ID bits [3..0] = revision -> discard during ID check */
28 #define PHY_MRVL_PHY_ID_MODEL_MASK 0xFFFFFFF0
29 #define PHY_MRVL_PHY_ID_MODEL_88E1111 0x01410CC0
30 #define PHY_MRVL_PHY_ID_MODEL_88E151X 0x01410DD0
32 #define PHY_MRVL_BASE_REGISTERS_PAGE 0
33 #define PHY_MRVL_COPPER_CONTROL_REGISTER 0
57 #define PHY_MRVL_ADV_SELECTOR_802_3 0x0001
59 #define PHY_MRVL_MDIX_CONFIG_MASK 0x0003
61 #define PHY_MRVL_MDIX_AUTO_CROSSOVER_ENABLE 0x0003
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/Zephyr-latest/arch/sparc/core/
Dreset_trap.S37 and %g1, 0xfffffff0, %l3
50 set 0xaaaaaaaa, %l0
72 ta 0x00
/Zephyr-latest/tests/boards/intel_adsp/smoke/src/
Dipm.c11 #define ID_INBOUND 0xfffffff0
12 #define ID_INVALID 0xffffffff
14 static K_SEM_DEFINE(ipm_sem, 0, 1);
37 * message with msg[0] as the ID (on cAVS 1.8+, otherwise in msg_transact()
47 IS_ENABLED(IPM_CAVS_HOST_REGWORD) ? msg[0] : 0, in msg_transact()
61 for (int i = 0; i < ARRAY_SIZE(msg); i++) { in msg_transact()
67 for (int i = 0; i < ARRAY_SIZE(msg); i++) { in msg_transact()
/Zephyr-latest/soc/snps/arc_iot/
Dsysconf.c59 /* 0x52000000 is not described in spec. */ in arc_iot_pll_conf_reg()
60 sysconf_reg_ptr->PLLCON = val | (0x52000000); in arc_iot_pll_conf_reg()
73 sysconf_reg_ptr->AHBCLKDIV = 0x1; in arc_iot_pll_conf_reg()
84 for (i = 0U; i < ARRAY_SIZE(pll_configuration); i++) { in arc_iot_pll_fout_config()
103 return 0; in arc_iot_pll_fout_config()
161 (sysconf_reg_ptr->SPI_MST_CLKDIV & 0xffffff00) | div; in arc_iot_spi_master_clk_divisor()
164 (sysconf_reg_ptr->SPI_MST_CLKDIV & 0xffff00ff) | (div << 8); in arc_iot_spi_master_clk_divisor()
167 (sysconf_reg_ptr->SPI_MST_CLKDIV & 0xff00ffff) | (div << 16); in arc_iot_spi_master_clk_divisor()
175 (sysconf_reg_ptr->GPIO8B_DBCLK_DIV & 0xffffff00) | div; in arc_iot_gpio8b_dbclk_div()
178 (sysconf_reg_ptr->GPIO8B_DBCLK_DIV & 0xffff00ff) | (div << 8); in arc_iot_gpio8b_dbclk_div()
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/Zephyr-latest/tests/kernel/mem_protect/syscalls/src/
Dmain.c25 #define FAULTY_ADDRESS 0x0FFFFFFF
27 #define FAULTY_ADDRESS 0xBFFFFFFF
32 #define FAULTY_ADDRESS 0xFFFFFFF0
71 return 0; in z_impl_string_alloc_copy()
97 return 0; in z_impl_string_copy()
121 return 0; in z_impl_to_copy()
135 return (int)(arg + 0x8c32a9eda4ca2621ULL + (size_t)&kernel_string); in z_impl_syscall_arg64()
153 uint64_t ret = 0xae751a24ef464cc0ULL; in z_impl_syscall_arg64_big()
155 for (int i = 0; i < ARRAY_SIZE(args); i++) { in z_impl_syscall_arg64_big()
175 uint32_t ret = 0x4ef464cc; in z_impl_more_args()
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/Zephyr-latest/tests/kernel/timer/timer_api/src/
Dtimer_convert.c235 __ASSERT(0, ""); in get_hz()
236 return 0; in get_hz()
266 * 0 ==? val * to_hz - result * from_hz in test_conversion()
268 * The difference is allowed to be in the range [0:from_hz) if in test_conversion()
269 * we are rounding down, from (-from_hz:0] if we are rounding in test_conversion()
278 mindiff = 0; in test_conversion()
280 maxdiff = 0; in test_conversion()
296 for (int i = 0; i < ARRAY_SIZE(tests); i++) { in ZTEST()
297 test_conversion(&tests[i], 0); in ZTEST()
299 test_conversion(&tests[i], 0x7fffffff); in ZTEST()
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/Zephyr-latest/tests/kernel/threads/thread_apis/src/
Dmain.c89 K_PRIO_COOP(1), 0, K_NO_WAIT); in ZTEST()
115 zassert_equal(ret, 0, "k_thread_name_set() failed"); in ZTEST()
119 zassert_equal(ret, 0, "parent thread name does not match"); in ZTEST()
124 K_PRIO_PREEMPT(1), 0, K_NO_WAIT); in ZTEST()
127 zassert_equal(ret, 0, "k_thread_name_set() failed"); in ZTEST()
129 zassert_equal(ret, 0, "couldn't get copied thread name"); in ZTEST()
131 zassert_equal(ret, 0, "child thread name does not match"); in ZTEST()
160 ret = k_thread_name_set(NULL, (const char *)0xFFFFFFF0); in ZTEST_USER()
172 zassert_equal(ret, 0, "k_thread_name_set() failed"); in ZTEST_USER()
175 zassert_equal(ret, 0, "k_thread_name_copy() failed"); in ZTEST_USER()
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/Zephyr-latest/dts/common/nordic/
Dnrf54h20.dtsi26 #size-cells = <0>;
59 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>,
77 nordic,tasks-mask = <0xfffffff0>;
93 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>,
127 nordic,tasks-mask = <0xffff0000>;
132 // substate-id = <0>; is reserved for "idle", cache powered on
155 reg = <0xe1ed000 DT_SIZE_K(20)>;
163 #clock-cells = <0>;
170 #clock-cells = <0>;
176 #clock-cells = <0>;
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/Zephyr-latest/tests/kernel/common/src/
Dbitarray.c17 #define BIT_INDEX(bit) ((3 - ((bit >> 3) & 0x3)) + 4*(bit >> 5))
21 #define BIT_VAL(bit) (1 << (bit & 0x7))
35 for (i = 0; i < sz; i++) { in cmp_u32_arrays()
38 printk("%s: [%zu] 0x%x != 0x%x", __func__, in cmp_u32_arrays()
51 #define FREE 0U
69 for (i = 0; i < num_bundles; i++) { in validate_bitarray_define()
109 for (i = 0; i < ba->num_bundles; i++) { in bitarray_bundles_is_zero()
110 if (ba->bundles[i] != 0) { in bitarray_bundles_is_zero()
141 for (bit = 0U; bit < ba.num_bits; ++bit) { in ZTEST()
142 bundle_idx = bit / (sizeof(ba.bundles[0]) * 8); in ZTEST()
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/Zephyr-latest/soc/intel/intel_adsp/tools/
Dcavstool.py27 # Window 0 is the FW_STATUS area, and 4k after that the IPC "outbox"
32 WINDOW_BASE = 0x80000
33 WINDOW_STRIDE = 0x20000
35 WINDOW_BASE_ACE = 0x180000
36 WINDOW_STRIDE_ACE = 0x8000
39 DEBUG_SLOT_SHELL = 0
46 CRST = 0
55 self.base = hdamem + 0x0080 + (stream_id * 0x20)
59 self.hda.GCAP = 0x0000
60 self.hda.GCTL = 0x0008
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