Lines Matching +full:0 +full:xfffffff0
26 #size-cells = <0>;
59 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>,
77 nordic,tasks-mask = <0xfffffff0>;
93 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>,
127 nordic,tasks-mask = <0xffff0000>;
132 // substate-id = <0>; is reserved for "idle", cache powered on
155 reg = <0xe1ed000 DT_SIZE_K(20)>;
163 #clock-cells = <0>;
170 #clock-cells = <0>;
176 #clock-cells = <0>;
187 #clock-cells = <0>;
197 #clock-cells = <0>;
218 reg = <0xe000000 DT_SIZE_K(2048)>;
226 reg = <0xfff8000 DT_SIZE_K(2)>;
229 ranges = <0x0 0xfff8000 DT_SIZE_K(2)>;
234 reg = <0x7b0 48>;
240 reg = <0xfffa000 DT_SIZE_K(2)>;
246 reg = <0xfffe000 DT_SIZE_K(2)>;
252 reg = <0x22000000 DT_SIZE_K(32)>;
255 ranges = <0x0 0x22000000 0x8000>;
260 reg = <0x23000000 DT_SIZE_K(192)>;
263 ranges = <0x0 0x23000000 0x30000>;
269 ranges = <0x0 0x52000000 0x1000000>;
273 #clock-cells = <0>;
274 reg = <0xd000 0x1000>;
286 reg = <0x13000 0x1000>;
295 reg = <0x14000 0x1000>;
303 reg = <0x15000 0x1000>;
311 reg = <0x1e000 0x1000>;
323 ranges = <0x0 0x53000000 0x1000000>;
327 #clock-cells = <0>;
328 reg = <0xd000 0x1000>;
340 reg = <0x13000 0x1000>;
348 reg = <0x14000 0x1000>;
356 reg = <0x1e000 0x1000>;
361 reg = <0x22000 0x1000>;
367 reg = <0x24000 0x1000>;
376 reg = <0x25000 0x1000>;
383 reg = <0x28000 0x1000>;
390 prescaler = <0>;
395 reg = <0x29000 0x1000>;
402 prescaler = <0>;
407 reg = <0x2a000 0x1000>;
414 prescaler = <0>;
419 reg = <0x2b000 0x1000>;
430 reg = <0x2c000 0x1000>;
448 reg = <0x3a000 0x1000>;
455 reg = <0x3b000 0x1000>;
462 reg = <0x3c000 0x1000>;
469 reg = <0x3d000 0x1000>;
478 ranges = <0x0 0xbf000000 0x1000000>;
482 reg = <0x3000 0x408>;
489 reg = <0x1000 0x10>;
497 ranges = <0x0 0x5f000000 0x1000000>;
501 reg = <0x86000 0x1000>, <0x2f700000 0x40000>;
507 ghwcfg1 = <0xaa555000>;
508 ghwcfg2 = <0x22abfc72>;
509 ghwcfg4 = <0x1e10aa60>;
516 #size-cells = <0>;
517 reg = <0x95000 0x500 0x95500 0xb00>;
528 reg = <0x99000 0x1000>;
535 reg = <0x9a000 0x1000>;
542 reg = <0x9b000 0x1000>;
550 reg = <0x8c2000 0x1000>;
553 #clock-cells = <0>;
555 nordic,frequency = <0>;
557 nordic,out-drive = <0>;
566 reg = <0x8c8000 0x1000>;
570 nordic,tasks-mask = <0xfffff0ff>;
575 reg = <0x8d1000 0x1000>;
583 reg = <0x8d4000 0x1000>;
588 ranges = <0x0 0x8d4000 0x1000>;
590 cpuflpr_vevif_tx: mailbox@0 {
592 reg = <0x0 0x1000>;
596 nordic,tasks-mask = <0xffff0000>;
602 reg = <0x8d8000 0x400>, <0x2fbef800 0x800>, <0x2fbe8000 0x7800>;
607 bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
613 reg = <0x8e1000 0x1000>;
620 reg = <0x8e2000 0x1000>;
627 prescaler = <0>;
632 reg = <0x8e3000 0x1000>;
639 prescaler = <0>;
644 reg = <0x8e4000 0x1000>;
654 reg = <0x8e6000 0x1000>;
662 #size-cells = <0>;
671 reg = <0x8e6000 0x1000>;
682 reg = <0x8e7000 0x1000>;
690 #size-cells = <0>;
699 reg = <0x908000 0x1000>;
703 ranges = <0x0 0x908000 0x1000>;
706 cpuppr_vevif_tx: mailbox@0 {
708 reg = <0x0 0x1000>;
712 nordic,tasks-mask = <0xfffffff0>;
718 reg = <0x921000 0x1000>;
727 reg = <0x922000 0x1000>;
734 reg = <0x928000 0x1000>;
746 reg = <0x929000 0x1000>;
758 reg = <0x92b000 0x1000>;
767 reg = <0x92c000 0x1000>;
776 reg = <0x92d000 0x1000>;
784 reg = <0x934000 0x1000>;
792 reg = <0x938000 0x200>;
799 port = <0>;
804 reg = <0x938200 0x200>;
816 reg = <0x938400 0x200>;
828 reg = <0x938c00 0x200>;
841 reg = <0x938e00 0x200>;
854 reg = <0x939200 0x200>;
866 reg = <0x981000 0x1000>;
873 reg = <0x982000 0x1000>;
886 reg = <0x983000 0x1000>;
894 reg = <0x984000 0x1000>;
902 reg = <0x985000 0x1000>;
910 reg = <0x991000 0x1000>;
917 reg = <0x993000 0x1000>;
926 reg = <0x994000 0x1000>;
934 reg = <0x995000 0x1000>;
942 reg = <0x99c000 0x1000>;
955 reg = <0x9a1000 0x1000>;
962 reg = <0x9a2000 0x1000>;
969 prescaler = <0>;
974 reg = <0x9a3000 0x1000>;
981 prescaler = <0>;
986 reg = <0x9a4000 0x1000>;
996 reg = <0x9a5000 0x1000>;
1003 #size-cells = <0>;
1011 reg = <0x9a5000 0x1000>;
1019 #size-cells = <0>;
1030 reg = <0x9a5000 0x1000>;
1042 reg = <0x9a6000 0x1000>;
1049 #size-cells = <0>;
1057 reg = <0x9a6000 0x1000>;
1065 #size-cells = <0>;
1076 reg = <0x9a6000 0x1000>;
1088 reg = <0x9b1000 0x1000>;
1095 reg = <0x9b2000 0x1000>;
1102 prescaler = <0>;
1107 reg = <0x9b3000 0x1000>;
1114 prescaler = <0>;
1119 reg = <0x9b4000 0x1000>;
1129 reg = <0x9b5000 0x1000>;
1136 #size-cells = <0>;
1144 reg = <0x9b5000 0x1000>;
1152 #size-cells = <0>;
1163 reg = <0x9b5000 0x1000>;
1175 reg = <0x9b6000 0x1000>;
1182 #size-cells = <0>;
1190 reg = <0x9b6000 0x1000>;
1198 #size-cells = <0>;
1209 reg = <0x9b6000 0x1000>;
1221 reg = <0x9c1000 0x1000>;
1228 reg = <0x9c2000 0x1000>;
1235 prescaler = <0>;
1240 reg = <0x9c3000 0x1000>;
1247 prescaler = <0>;
1252 reg = <0x9c4000 0x1000>;
1262 reg = <0x9c5000 0x1000>;
1269 #size-cells = <0>;
1277 reg = <0x9c5000 0x1000>;
1285 #size-cells = <0>;
1296 reg = <0x9c5000 0x1000>;
1308 reg = <0x9c6000 0x1000>;
1315 #size-cells = <0>;
1323 reg = <0x9c6000 0x1000>;
1331 #size-cells = <0>;
1342 reg = <0x9c6000 0x1000>;
1354 reg = <0x9d1000 0x1000>;
1361 reg = <0x9d2000 0x1000>;
1368 prescaler = <0>;
1373 reg = <0x9d3000 0x1000>;
1380 prescaler = <0>;
1385 reg = <0x9d4000 0x1000>;
1395 reg = <0x9d5000 0x1000>;
1402 #size-cells = <0>;
1410 reg = <0x9d5000 0x1000>;
1418 #size-cells = <0>;
1429 reg = <0x9d5000 0x1000>;
1441 reg = <0x9d6000 0x1000>;
1448 #size-cells = <0>;
1456 reg = <0x9d6000 0x1000>;
1464 #size-cells = <0>;
1475 reg = <0x9d6000 0x1000>;
1493 reg = <0xe000e010 0x10>;
1499 reg = <0xe000e100 0xc00>;
1513 reg = <0xe000e010 0x10>;
1519 reg = <0xe000e100 0xc00>;
1533 reg = <0xf0000000 0x3000>;
1547 reg = <0xf0000000 0x3000>;