Lines Matching +full:0 +full:xfffffff0
17 #define PHY_XLNX_GEM_EVENT_LINK_SPEED_CHANGED (1 << 0)
27 /* Marvell PHY ID bits [3..0] = revision -> discard during ID check */
28 #define PHY_MRVL_PHY_ID_MODEL_MASK 0xFFFFFFF0
29 #define PHY_MRVL_PHY_ID_MODEL_88E1111 0x01410CC0
30 #define PHY_MRVL_PHY_ID_MODEL_88E151X 0x01410DD0
32 #define PHY_MRVL_BASE_REGISTERS_PAGE 0
33 #define PHY_MRVL_COPPER_CONTROL_REGISTER 0
57 #define PHY_MRVL_ADV_SELECTOR_802_3 0x0001
59 #define PHY_MRVL_MDIX_CONFIG_MASK 0x0003
61 #define PHY_MRVL_MDIX_AUTO_CROSSOVER_ENABLE 0x0003
62 #define PHY_MRVL_MODE_CONFIG_MASK 0x0007
63 #define PHY_MRVL_MODE_CONFIG_SHIFT 0
72 #define PHY_MRVL_LINK_SPEED_MASK 0x3
73 #define PHY_MRVL_LINK_SPEED_10MBIT 0
79 /* TI PHY ID bits [3..0] = revision -> discard during ID check */
80 #define PHY_TI_PHY_ID_MODEL_MASK 0xFFFFFFF0
81 #define PHY_TI_PHY_ID_MODEL_DP83822 0x2000A240
82 #define PHY_TI_PHY_ID_MODEL_TLK105 0x2000A210
84 #define PHY_TI_PHY_SPECIFIC_CONTROL_REGISTER 0x0010
85 #define PHY_TI_BASIC_MODE_CONTROL_REGISTER 0x0000
86 #define PHY_TI_BASIC_MODE_STATUS_REGISTER 0x0001
87 #define PHY_TI_AUTONEG_ADV_REGISTER 0x0004
88 #define PHY_TI_CONTROL_REGISTER_1 0x0009
89 #define PHY_TI_PHY_STATUS_REGISTER 0x0010
90 #define PHY_TI_MII_INTERRUPT_STATUS_REGISTER_1 0x0012
91 #define PHY_TI_LED_CONTROL_REGISTER 0x0018
92 #define PHY_TI_PHY_CONTROL_REGISTER 0x0019
104 #define PHY_TI_ADV_SELECTOR_802_3 0x0001
117 #define PHY_TI_LED_CONTROL_BLINK_RATE_20HZ 0
122 #define PHY_TI_PHY_STATUS_LINK_BIT (1 << 0)