1/*
2 * Copyright (c) 2019-2020 Cobham Gaisler AB
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/toolchain.h>
8#include <zephyr/linker/sections.h>
9#include <zephyr/arch/sparc/sparc.h>
10
11/* The trap table reset entry jumps to here. */
12
13GTEXT(__sparc_trap_reset)
14SECTION_FUNC(TEXT, __sparc_trap_reset)
15#ifdef CONFIG_SPARC_SVT
16#ifdef CONFIG_SOC_SPARC_LEON
17	/* On LEON, enable single vector trapping by setting ASR17.SV. */
18	rd	%asr17, %g1
19	set	(1<<13), %g2
20	or	%g1, %g2, %g1
21	wr	%g1, %asr17
22#else
23#error "Don't know how to enable SVT on this SOC"
24#endif
25#endif
26
27	set	__sparc_trap_table, %g1
28	wr	%g1, %tbr
29	wr	2, %wim
30	wr	PSR_PIL | PSR_S | PSR_PS | PSR_ET, %psr
31	/* NOTE: wrpsr above may have changed the current register window. */
32
33	/* We are in the 3 instruction wrpsr delay so use global registers. */
34	set	z_interrupt_stacks, %g2
35	set	CONFIG_ISR_STACK_SIZE, %g4
36	add	%g2, %g4, %g1
37	and	%g1, 0xfffffff0, %l3
38
39	/*
40	 * According to SPARC ABI, Chapter 3: The system marks the deepest
41	 * stack frame by setting the frame pointer to zero. No other frame's
42	 * %fp has a zero value.
43	 */
44	sub	%l3, 96, %sp
45	clr	%fp
46	clr	%i7
47
48#ifdef CONFIG_INIT_STACKS
49	/* In-place memset() to avoid register window related traps. */
50	set	0xaaaaaaaa, %l0
51	mov	%l0, %l1
521:
53	std	%l0, [%g2]
54	add	%g2, 8, %g2
55	cmp	%g2, %l3
56	bne	1b
57	 nop
58#endif
59
60	call	z_bss_zero
61	 nop
62
63	call    z_prep_c
64	 nop
65
66/* We halt the system by generating a "trap in trap" condition. */
67GTEXT(arch_system_halt)
68SECTION_FUNC(TEXT, arch_system_halt)
69	mov	%o0, %g0
70	mov	%g1, %g0
71	set	1, %g1
72	ta	0x00
73