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/Zephyr-latest/include/zephyr/dt-bindings/sensor/
Dlsm6dsv16x.h10 #define LSM6DSV16X_DT_FS_2G 0
16 #define LSM6DSV16X_DT_FS_125DPS 0x0
17 #define LSM6DSV16X_DT_FS_250DPS 0x1
18 #define LSM6DSV16X_DT_FS_500DPS 0x2
19 #define LSM6DSV16X_DT_FS_1000DPS 0x3
20 #define LSM6DSV16X_DT_FS_2000DPS 0x4
21 #define LSM6DSV16X_DT_FS_4000DPS 0xc
24 #define LSM6DSV16X_DT_ODR_OFF 0x0
25 #define LSM6DSV16X_DT_ODR_AT_1Hz875 0x1
26 #define LSM6DSV16X_DT_ODR_AT_7Hz5 0x2
[all …]
Dism330dhcx.h10 #define ISM330DHCX_DT_ODR_OFF 0x0
11 #define ISM330DHCX_DT_ODR_12Hz5 0x1
12 #define ISM330DHCX_DT_ODR_26H 0x2
13 #define ISM330DHCX_DT_ODR_52Hz 0x3
14 #define ISM330DHCX_DT_ODR_104Hz 0x4
15 #define ISM330DHCX_DT_ODR_208Hz 0x5
16 #define ISM330DHCX_DT_ODR_416Hz 0x6
17 #define ISM330DHCX_DT_ODR_833Hz 0x7
18 #define ISM330DHCX_DT_ODR_1666Hz 0x8
19 #define ISM330DHCX_DT_ODR_3332Hz 0x9
[all …]
Dlsm6dso.h10 #define LSM6DSO_DT_XL_HP_MODE 0
15 #define LSM6DSO_DT_GY_HP_MODE 0
19 #define LSM6DSO_DT_FS_2G 0
25 #define LSM6DSO_DT_FS_250DPS 0
32 #define LSM6DSO_DT_ODR_OFF 0x0
33 #define LSM6DSO_DT_ODR_12Hz5 0x1
34 #define LSM6DSO_DT_ODR_26H 0x2
35 #define LSM6DSO_DT_ODR_52Hz 0x3
36 #define LSM6DSO_DT_ODR_104Hz 0x4
37 #define LSM6DSO_DT_ODR_208Hz 0x5
[all …]
Dtmag5273.h12 #define TMAG5273_DT_OPER_MODE_CONTINUOUS 0
16 #define TMAG5273_DT_AXIS_NONE 0x0
17 #define TMAG5273_DT_AXIS_X 0x1
18 #define TMAG5273_DT_AXIS_Y 0x2
19 #define TMAG5273_DT_AXIS_Z 0x4
24 #define TMAG5273_DT_AXIS_XYX 0x8
25 #define TMAG5273_DT_AXIS_YXY 0x9
26 #define TMAG5273_DT_AXIS_YZY 0xA
27 #define TMAG5273_DT_AXIS_XZX 0xB
30 #define TMAG5273_DT_AXIS_RANGE_LOW 0
[all …]
/Zephyr-latest/scripts/dts/python-devicetree/tests/
Dtest.dts29 controller-0 {
46 &{/interrupts-extended-test/controller-0} 1
53 #size-cells = <0>;
55 controller-0 {
76 0 0 0 0 &{/interrupt-map-test/controller-0} 0 0
77 0 0 0 1 &{/interrupt-map-test/controller-1} 0 0 0 1
78 0 0 0 2 &{/interrupt-map-test/controller-2} 0 0 0 0 0 2
79 0 1 0 0 &{/interrupt-map-test/controller-0} 0 3
80 0 1 0 1 &{/interrupt-map-test/controller-1} 0 0 0 4
81 0 1 0 2 &{/interrupt-map-test/controller-2} 0 0 0 0 0 5>;
[all …]
/Zephyr-latest/include/zephyr/arch/arc/v2/
Dexception.h26 #define ARC_EV_RESET 0x0
27 #define ARC_EV_MEM_ERROR 0x1
28 #define ARC_EV_INS_ERROR 0x2
29 #define ARC_EV_MACHINE_CHECK 0x3
30 #define ARC_EV_TLB_MISS_I 0x4
31 #define ARC_EV_TLB_MISS_D 0x5
32 #define ARC_EV_PROT_V 0x6
33 #define ARC_EV_PRIVILEGE_V 0x7
34 #define ARC_EV_SWI 0x8
35 #define ARC_EV_TRAP 0x9
[all …]
/Zephyr-latest/dts/bindings/i2c/
Datmel,sam0-i2c.yaml32 dmas = <&dmac 0 0xb>, <&dmac 0 0xa>;
/Zephyr-latest/dts/bindings/spi/
Datmel,sam0-spi.yaml39 dmas = <&dmac 0 0xb>, <&dmac 1 0xa>;
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-ra.h10 #define RA_PORT_NUM_POS 0
11 #define RA_PORT_NUM_MASK 0xf
14 #define RA_PIN_NUM_MASK 0xf
16 #define RA_PSEL_HIZ_JTAG_SWD 0x0
17 #define RA_PSEL_AGT 0x1
18 #define RA_PSEL_GPT0 0x2
19 #define RA_PSEL_GPT1 0x3
20 #define RA_PSEL_SCI_0 0x4
21 #define RA_PSEL_SCI_2 0x4
22 #define RA_PSEL_SCI_4 0x4
[all …]
/Zephyr-latest/include/zephyr/drivers/firmware/scmi/
Dclk.h17 #define SCMI_CLK_CONFIG_DISABLE_ENABLE_MASK GENMASK(1, 0)
21 #define SCMI_CLK_ATTRIBUTES_CLK_NUM(x) ((x) & GENMASK(15, 0))
39 SCMI_CLK_MSG_PROTOCOL_VERSION = 0x0,
40 SCMI_CLK_MSG_PROTOCOL_ATTRIBUTES = 0x1,
41 SCMI_CLK_MSG_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2,
42 SCMI_CLK_MSG_CLOCK_ATTRIBUTES = 0x3,
43 SCMI_CLK_MSG_CLOCK_DESCRIBE_RATES = 0x4,
44 SCMI_CLK_MSG_CLOCK_RATE_SET = 0x5,
45 SCMI_CLK_MSG_CLOCK_RATE_GET = 0x6,
46 SCMI_CLK_MSG_CLOCK_CONFIG_SET = 0x7,
[all …]
/Zephyr-latest/drivers/sensor/maxim/max17055/
Dmax17055.h14 STATUS = 0x0,
15 REP_CAP = 0x5,
16 REP_SOC = 0x6,
17 INT_TEMP = 0x8,
18 VCELL = 0x9,
19 AVG_CURRENT = 0xb,
20 FULL_CAP_REP = 0x10,
21 TTE = 0x11,
22 ICHG_TERM = 0x1e,
23 CYCLES = 0x17,
[all …]
/Zephyr-latest/subsys/usb/device_next/class/
Dusbd_msc_scsi.h20 GOOD = 0x00,
21 CHECK_CONDITION = 0x02,
22 CONDITION_MET = 0x04,
23 BUSY = 0x08,
24 RESERVATION_CONFLICT = 0x18,
25 TASK_SET_FULL = 0x28,
26 ACA_ACTIVE = 0x30,
27 TASK_ABORTED = 0x40,
34 NO_SENSE = 0x0,
35 RECOVERED_ERROR = 0x1,
[all …]
/Zephyr-latest/tests/drivers/build_all/led/
Dapp.overlay21 reg = <0xdeadbeef 0x1000>;
22 #gpio-cells = <0x2>;
29 gpios = <&test_gpio 0 0>;
35 #size-cells = <0>;
37 reg = <0x11112222 0x1000>;
43 reg = <0x1>;
45 #size-cells = <0>;
50 reg = <0x2>;
55 reg = <0x3>;
60 reg = <0x4>;
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dstm32-pinctrl.h18 #define STM32_AF0 0x0
19 #define STM32_AF1 0x1
20 #define STM32_AF2 0x2
21 #define STM32_AF3 0x3
22 #define STM32_AF4 0x4
23 #define STM32_AF5 0x5
24 #define STM32_AF6 0x6
25 #define STM32_AF7 0x7
26 #define STM32_AF8 0x8
27 #define STM32_AF9 0x9
[all …]
/Zephyr-latest/drivers/dma/
Ddma_iproc_pax_v2.h12 #define RING_COMPLETION_INTERRUPT_STAT_MASK 0x088
13 #define RING_COMPLETION_INTERRUPT_STAT_CLEAR 0x08c
14 #define RING_COMPLETION_INTERRUPT_STAT 0x090
15 #define RING_DISABLE_MSI_TIMEOUT 0x0a4
18 #define RM_COMM_CONTROL_MODE_MASK 0x3
19 #define RM_COMM_CONTROL_MODE_SHIFT 0
20 #define RM_COMM_CONTROL_MODE_DOORBELL 0x0
21 #define RM_COMM_CONTROL_MODE_TOGGLE 0x2
22 #define RM_COMM_CONTROL_MODE_ALL_BD_TOGGLE 0x3
29 #define PAX_DMA_TYPE_SRC_DESC 0x2
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dst,lsm6dsv16x-common.yaml12 lsm6dsv16x: lsm6dsv16x@0 {
58 default: 0
62 - 0 # LSM6DSV16X_DT_FS_2G (0.061 mg/LSB)
67 enum: [0, 1, 2, 3]
71 default: 0x0
79 - 0x00 # LSM6DSV16X_DT_ODR_OFF
80 - 0x01 # LSM6DSV16X_DT_ODR_AT_1Hz875
81 - 0x02 # LSM6DSV16X_DT_ODR_AT_7Hz5
82 - 0x03 # LSM6DSV16X_DT_ODR_AT_15Hz
83 - 0x04 # LSM6DSV16X_DT_ODR_AT_30Hz
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_max14916.h12 #define MAX14906_DISABLE 0
18 #define MAX14916_SETOUT_REG 0x0
19 #define MAX14916_SET_FLED_REG 0x1
20 #define MAX14916_SET_SLED_REG 0x2
21 #define MAX14916_INT_REG 0x3
22 #define MAX14916_OVR_LD_REG 0x4
23 #define MAX14916_CURR_LIM_REG 0x5
24 #define MAX14916_OW_OFF_FLT_REG 0x6
25 #define MAX14916_OW_ON_FLT_REG 0x7
26 #define MAX14916_SHT_VDD_FLT_REG 0x8
[all …]
/Zephyr-latest/drivers/watchdog/
Dwdt_nxp_fs26.h13 #define FS26_M_FS (0x1 << 31)
16 #define FS26_REG_ADDR_MASK (0x7f << FS26_REG_ADDR_SHIFT)
19 /* Read/Write (reading = 0) */
20 #define FS26_RW (0x1 << 24)
26 #define FS26_DEV_STATUS_MASK (0xff << FS26_DEV_STATUS_SHIFT)
29 #define FS26_M_AVAL (0x1 << 31)
31 #define FS26_FS_EN (0x1 << 30)
33 #define FS26_FS_G (0x1 << 29)
35 #define FS26_COM_G (0x1 << 28)
37 #define FS26_WIO_G (0x1 << 27)
[all …]
/Zephyr-latest/include/zephyr/drivers/rtc/
Dmcp7940n.h133 REG_RTC_SEC = 0x0,
134 REG_RTC_MIN = 0x1,
135 REG_RTC_HOUR = 0x2,
136 REG_RTC_WDAY = 0x3,
137 REG_RTC_DATE = 0x4,
138 REG_RTC_MONTH = 0x5,
139 REG_RTC_YEAR = 0x6,
140 REG_RTC_CONTROL = 0x7,
141 REG_RTC_OSCTRIM = 0x8,
142 /* 0x9 not implemented */
[all …]
/Zephyr-latest/subsys/bluetooth/host/classic/
Davrcp_internal.h12 #define AVCTP_VER_1_4 (0x0104u)
13 #define AVRCP_VER_1_6 (0x0106u)
15 #define AVRCP_CAT_1 BIT(0) /* Player/Recorder */
20 #define AVRCP_SUBUNIT_PAGE (0) /* Fixed value according to AVRCP */
24 BT_AVRCP_CTYPE_CONTROL = 0x0,
25 BT_AVRCP_CTYPE_STATUS = 0x1,
26 BT_AVRCP_CTYPE_SPECIFIC_INQUIRY = 0x2,
27 BT_AVRCP_CTYPE_NOTIFY = 0x3,
28 BT_AVRCP_CTYPE_GENERAL_INQUIRY = 0x4,
29 BT_AVRCP_CTYPE_NOT_IMPLEMENTED = 0x8,
[all …]
/Zephyr-latest/tests/drivers/build_all/adc/boards/
Dnative_sim.overlay30 reg = <0xdeadbeef 0x1000>;
31 #gpio-cells = <0x2>;
37 #size-cells = <0>;
39 reg = <0x11112222 0x1000>;
43 test_i2c_ads1013: ads1013@0 {
45 reg = <0x0>;
51 reg = <0x1>;
52 alert-rdy-gpios = <&test_gpio 0 0>;
58 reg = <0x2>;
59 alert-rdy-gpios = <&test_gpio 0 0>;
[all …]
/Zephyr-latest/drivers/sensor/ltrf216a/
Dltrf216a.c25 * 7bit Address 0x53
26 * 8bit Address 0xA6 read
27 * 8bit Address 0xA7 write
42 /* Part Number ID 7:4 0b1011 = 0xB */
43 /* Revision ID 3:0 0b0001 = 0x1*/
44 #define LTRF216A_PART_ID_VALUE 0xB1
46 #define LTRF216A_MAIN_CTRL 0x00
47 #define LTRF216A_ALS_MEAS_RES 0x04
48 #define LTRF216A_ALS_GAIN 0x05
49 #define LTRF216A_PART_ID 0x06
[all …]
/Zephyr-latest/tests/drivers/sensor/adltc2990/boards/
Dnative_sim.overlay9 reg = <0x1>;
10 measurement-mode = <0 0>;
11 pins-v1-v2-current-resistor = <0>;
12 pins-v3-v4-current-resistor = <0>;
21 reg = <0xb>;
22 temperature-format = <0>;
26 pins-v3-v4-current-resistor = <0>;
27 pin-v1-voltage-divider-resistors = <0 1>;
28 pin-v2-voltage-divider-resistors = <0 1>;
29 pin-v3-voltage-divider-resistors = <0 1>;
[all …]
/Zephyr-latest/soc/atmel/sam0/common/
Dsoc_port.h19 #define SOC_PORT_DEFAULT (0)
21 #define SOC_PORT_FLAGS_POS (0)
22 #define SOC_PORT_FLAGS_MASK (0x7B << SOC_PORT_FLAGS_POS)
35 /* Drive-Strength, 0mA means normal, any other value means stronger */
44 #define SOC_PORT_FUNC_MASK (0xF << SOC_PORT_FUNC_POS)
47 #define SOC_PORT_FUNC_A (0x0 << SOC_PORT_FUNC_POS)
49 #define SOC_PORT_FUNC_B (0x1 << SOC_PORT_FUNC_POS)
51 #define SOC_PORT_FUNC_C (0x2 << SOC_PORT_FUNC_POS)
53 #define SOC_PORT_FUNC_D (0x3 << SOC_PORT_FUNC_POS)
55 #define SOC_PORT_FUNC_E (0x4 << SOC_PORT_FUNC_POS)
[all …]
/Zephyr-latest/arch/arc/core/mpu/
Darc_mpu_v2_internal.h14 * represented in [11:9] and the two LSB bits are represented in [1:0].
17 * 0x4 32 0x5 64 0x6 128 0x7 256
18 * 0x8 512 0x9 1k 0xA 2K 0xB 4K
19 * 0xC 8K 0xD 16K 0xE 32K 0xF 64K
20 * 0x10 128K 0x11 256K 0x12 512K 0x13 1M
21 * 0x14 2M 0x15 4M 0x16 8M 0x17 16M
22 * 0x18 32M 0x19 64M 0x1A 128M 0x1B 256M
23 * 0x1C 512M 0x1D 1G 0x1E 2G 0x1F 4G
25 * Bit ... 12 11 10 9 8 3 2 1 0
27 * ... | SIZE[11:9] | ATTR | R | SIZE[1:0] |
[all …]

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