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/Zephyr-latest/tests/subsys/storage/flash_map/src/
Dmain_sha.c25 uint8_t tst_vec[] = { 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, in ZTEST()
26 0x38, 0x39, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, in ZTEST()
27 0x0a, 0x66, 0x65, 0x64, 0x63, 0x62, 0x61, 0x39, in ZTEST()
28 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x0a, in ZTEST()
29 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, in ZTEST()
30 0x38, 0x39, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, in ZTEST()
31 0x0a, 0x66, 0x65, 0x64, 0x63, 0x62, 0x61, 0x39, in ZTEST()
32 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x0a, in ZTEST()
33 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, in ZTEST()
34 0x38, 0x39, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, in ZTEST()
[all …]
/Zephyr-latest/dts/bindings/mfd/
Dite,it8801-mfd.yaml15 * SMB_ADDR pin is 0, SMBus address is 0x38
16 * SMB_ADDR pin is 1, SMBus address is 0x39
18 reg = <0x38>;
19 irq-gpios = <&gpioa 1 0>; /* SMB_INT# */
33 kso-mapping = <0 1 20 3 4 5 6 17 18 16 15 11 12>;
/Zephyr-latest/dts/bindings/flash_controller/
Dst,stm32-ospi-nor.yaml11 reg = <0x70000000 DT_SIZE_M(64)>; /* 512 Mbits */
69 - "PP" # Page program, PP (0x02) up to 256 bytes
70 - "PP_1_1_2" # Dual page program, PP 1-1-2 (0xA2)
71 - "PP_1_1_4" # Quad data line SPI, PP 1-1-4 (0x32)
72 - "PP_1_4_4" # Quad data line SPI, PP 1-4-4 (0x38)
86 * OSPI_SPI_MODE -> PP 1-1-1 (0x02)
87 * OSPI_DUAL_MODE -> PP 1-1-2 (0xA2)
88 * OSPI_QUAD_MODE -> PP 1-4-4 (0x38)
98 * PP 1-1-1 (0x02) -> PP 1-1-1 4B (0x12)
99 * PP 1-1-4 (0x32) -> PP 1-1-4 4B (0x34)
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dstm32u0_reset.h13 #define STM32_RESET_BUS_IOP 0x2C
14 #define STM32_RESET_BUS_AHB1 0x28
15 #define STM32_RESET_BUS_APB1L 0x38
16 #define STM32_RESET_BUS_APB1H 0x40
Dstm32wb0_reset.h13 #define STM32_RESET_BUS_AHB0 0x30
14 #define STM32_RESET_BUS_APB0 0x34
15 #define STM32_RESET_BUS_APB1 0x38
16 #define STM32_RESET_BUS_APB2 0x3C
Dstm32g4_l4_5_reset.h13 #define STM32_RESET_BUS_AHB1 0x28
14 #define STM32_RESET_BUS_AHB2 0x2C
15 #define STM32_RESET_BUS_AHB3 0x30
16 #define STM32_RESET_BUS_APB1L 0x38
17 #define STM32_RESET_BUS_APB1H 0x3C
18 #define STM32_RESET_BUS_APB2 0x40
Dstm32wb_l_reset.h13 #define STM32_RESET_BUS_AHB1 0x28
14 #define STM32_RESET_BUS_AHB2 0x2C
15 #define STM32_RESET_BUS_AHB3 0x30
16 #define STM32_RESET_BUS_APB1L 0x38
17 #define STM32_RESET_BUS_APB1H 0x3C
18 #define STM32_RESET_BUS_APB2 0x40
19 #define STM32_RESET_BUS_APB3 0x44
/Zephyr-latest/lib/crc/
Dcrc8_sw.c12 0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
13 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d
17 0x00, 0x1c, 0x38, 0x24, 0x70, 0x6c, 0x48, 0x54,
18 0xe0, 0xfc, 0xd8, 0xc4, 0x90, 0x8c, 0xa8, 0xb4
26 for (i = 0; i < cnt; i++) { in crc8_ccitt()
39 for (i = 0; i < cnt; i++) { in crc8_rohc()
41 val = (val >> 4) ^ crc8_rohc_small_table[val & 0x0f]; in crc8_rohc()
42 val = (val >> 4) ^ crc8_rohc_small_table[val & 0x0f]; in crc8_rohc()
53 for (i = 0; i < len; i++) { in crc8()
56 for (j = 0; j < 8; j++) { in crc8()
[all …]
/Zephyr-latest/drivers/sensor/bosch/bmp581/
Dbmp581.h26 #define BMP5_SET_LOW_BYTE 0x00FFu
27 #define BMP5_SET_HIGH_BYTE 0xFF00u
45 #define BMP5_OK 0
47 #define BMP5_DISABLE 0u
50 #define BMP5_REG_CHIP_ID 0x01
51 #define BMP5_REG_REV_ID 0x02
52 #define BMP5_REG_CHIP_STATUS 0x11
53 #define BMP5_REG_DRIVE_CONFIG 0x13
54 #define BMP5_REG_INT_CONFIG 0x14
55 #define BMP5_REG_INT_SOURCE 0x15
[all …]
/Zephyr-latest/tests/drivers/build_all/gpio/
Dit82xx2_evb.overlay12 reg = <0x38>;
13 irq-gpios = <&gpioa 1 0>;
/Zephyr-latest/tests/kernel/fpu_sharing/generic/src/
Dfloat_regs_sparc.h16 "ldd [%0 + 0x00], %%f0\n" in _load_all_float_registers()
17 "ldd [%0 + 0x08], %%f2\n" in _load_all_float_registers()
18 "ldd [%0 + 0x10], %%f4\n" in _load_all_float_registers()
19 "ldd [%0 + 0x18], %%f6\n" in _load_all_float_registers()
20 "ldd [%0 + 0x20], %%f8\n" in _load_all_float_registers()
21 "ldd [%0 + 0x28], %%f10\n" in _load_all_float_registers()
22 "ldd [%0 + 0x30], %%f12\n" in _load_all_float_registers()
23 "ldd [%0 + 0x38], %%f14\n" in _load_all_float_registers()
24 "ldd [%0 + 0x40], %%f16\n" in _load_all_float_registers()
25 "ldd [%0 + 0x48], %%f18\n" in _load_all_float_registers()
[all …]
/Zephyr-latest/tests/drivers/build_all/pwm/boards/
Dit82xx2_evb.overlay9 pwm-0 = &ioex_it8801_pwm7;
18 reg = <0x38>;
19 irq-gpios = <&gpioa 1 0>;
/Zephyr-latest/tests/bsim/bluetooth/host/att/read_fill_buf/
Dcommon_defs.h9 BT_UUID_DECLARE_128(0xdb, 0x1f, 0xe2, 0x52, 0xf3, 0xc6, 0x43, 0x66, 0xb3, 0x92, 0x5d, \
10 0xc6, 0xe7, 0xc9, 0x59, 0x9d)
14 BT_UUID_DECLARE_128(0x3f, 0xa4, 0x7f, 0x44, 0x2e, 0x2a, 0x43, 0x05, 0xab, 0x38, 0x07, \
15 0x8d, 0x16, 0xbf, 0x99, 0xf1)
/Zephyr-latest/drivers/display/
Ddisplay_ist3931.h9 #define IST3931_CMD_NOP 0xe3
10 #define IST3931_CMD_IST_COMMAND_ENTRY 0x88
11 #define IST3931_CMD_EXIT_ENTRY 0xe3
12 #define IST3931_CMD_IST_COM_MAPPING 0x60
13 #define IST3931_CMD_POWER_CONTROL 0x2c
14 #define IST3931_CMD_BIAS 0x30
15 #define IST3931_CMD_CT 0xb1
16 #define IST3931_CMD_FRAME_CONTROL 0xb2
17 #define IST3931_CMD_SET_AX_ADD 0xc0
18 #define IST3931_CMD_SET_AY_ADD_LSB 0x00
[all …]
/Zephyr-latest/soc/cdns/sample_controller32/include/
Dxtensa-sample-controller32.ld48 dram1_0_seg : org = 0x3FFC0000, len = 0x20000
49 dram0_0_seg : org = 0x3FFE0000, len = 0x20000
50 iram0_0_seg : org = 0x40000000, len = 0x178
51 iram0_1_seg : org = 0x40000178, len = 0x8
52 iram0_2_seg : org = 0x40000180, len = 0x38
53 iram0_3_seg : org = 0x400001B8, len = 0x8
54 iram0_4_seg : org = 0x400001C0, len = 0x38
55 iram0_5_seg : org = 0x400001F8, len = 0x8
56 iram0_6_seg : org = 0x40000200, len = 0x38
57 iram0_7_seg : org = 0x40000238, len = 0x8
[all …]
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dclock_agilex_ll.h13 #define CLKMGR_OFFSET 0xffd10000
15 #define CLKMGR_CTRL 0x0
16 #define CLKMGR_STAT 0x4
17 #define CLKMGR_INTRCLR 0x14
20 #define CLKMGR_MAINPLL 0xffd10024
21 #define CLKMGR_MAINPLL_EN 0x0
22 #define CLKMGR_MAINPLL_BYPASS 0xc
23 #define CLKMGR_MAINPLL_MPUCLK 0x18
24 #define CLKMGR_MAINPLL_NOCCLK 0x1c
25 #define CLKMGR_MAINPLL_NOCDIV 0x20
[all …]
/Zephyr-latest/tests/drivers/build_all/input/
Dit82xx2_evb.overlay14 reg = <0x38>;
15 irq-gpios = <&gpioa 1 0>;
25 kso-mapping = <0 1 20 3 4 5 6 17 18 16 15 11 12>;
/Zephyr-latest/arch/sparc/core/
Dwindow_trap.S25 std %l0, [%sp + 0x00]
26 std %l2, [%sp + 0x08]
27 std %l4, [%sp + 0x10]
29 std %l6, [%sp + 0x18]
33 std %i0, [%sp + 0x20]
36 std %i2, [%sp + 0x28]
40 std %i4, [%sp + 0x30]
42 std %i6, [%sp + 0x38]
65 ldd [%sp + 0x00], %l0
66 ldd [%sp + 0x08], %l2
[all …]
/Zephyr-latest/dts/bindings/mtd/
Dnxp,s32-qspi-nor.yaml20 - "1-1-1" # 0x0B
21 - "1-1-2" # 0x3B
22 - "1-2-2" # 0xBB
23 - "1-1-4" # 0x6B
24 - "1-4-4" # 0xEB
32 - "1-1-1" # 0x02
33 - "1-1-2" # 0xA2
34 - "1-1-4" # 0x32
35 - "1-4-4" # 0x38
/Zephyr-latest/drivers/gpio/
Dgpio_dw_registers.h15 #define SWPORTA_DR 0x00
16 #define SWPORTA_DDR 0x04
17 #define SWPORTA_CTL 0x08
18 #define SWPORTB_DR 0x0c
19 #define SWPORTB_DDR 0x10
20 #define SWPORTB_CTL 0x14
21 #define SWPORTC_DR 0x18
22 #define SWPORTC_DDR 0x1c
23 #define SWPORTC_CTL 0x20
24 #define SWPORTD_DR 0x24
[all …]
/Zephyr-latest/soc/intel/intel_adsp/common/include/
Dadsp-vectors.h13 #define MEM_VECBASE_LIT_SIZE 0x178
48 #define VECTOR_TBL_SIZE 0x1000
51 #define MEM_VECT_LIT_SIZE 0x8
52 #define MEM_VECT_TEXT_SIZE 0x38
54 #define MEM_ERROR_TEXT_SIZE 0x180
55 #define MEM_ERROR_LIT_SIZE 0x8
/Zephyr-latest/soc/cdns/xtensa_sample_controller/include/
Dxtensa-sample-controller.ld24 dram1_0_seg : org = 0x3FFC0000, len = 0x20000
25 dram0_0_seg : org = 0x3FFE0000, len = 0x20000
26 iram0_0_seg : org = 0x40000000, len = 0x178
27 iram0_1_seg : org = 0x40000178, len = 0x8
28 iram0_2_seg : org = 0x40000180, len = 0x38
29 iram0_3_seg : org = 0x400001B8, len = 0x8
30 iram0_4_seg : org = 0x400001C0, len = 0x38
31 iram0_5_seg : org = 0x400001F8, len = 0x8
32 iram0_6_seg : org = 0x40000200, len = 0x38
33 iram0_7_seg : org = 0x40000238, len = 0x8
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_agilex5_ll.h19 #define CLKCTRL_OFFSET 0x00
20 #define CLKCTRL_CTRL 0x00
21 #define CLKCTRL_STAT 0x04
22 #define CLKCTRL_TESTIOCTRL 0x08
23 #define CLKCTRL_INTRGEN 0x0C
24 #define CLKCTRL_INTRMSK 0x10
25 #define CLKCTRL_INTRCLR 0x14
26 #define CLKCTRL_INTRSTS 0x18
27 #define CLKCTRL_INTRSTK 0x1C
28 #define CLKCTRL_INTRRAW 0x20
[all …]
/Zephyr-latest/tests/subsys/dfu/img_util/src/
Dmain.c26 zassert_true(ret == 0, "Flash img init"); in ZTEST()
29 zassert_true(ret == 0, "Flash img init id"); in ZTEST()
37 zassert_true(ret == 0, "Flash img init id"); in ZTEST()
52 zassert_true(ret == 0, "Flash img init"); in ZTEST()
56 (void)memset(erase_buf, 0xff, sizeof(erase_buf)); in ZTEST()
65 for (i = 0U; i < 300 * sizeof(data) / sizeof(erase_buf); i++) { in ZTEST()
68 zassert_true(ret == 0, "Flash write failure (%d)", ret); in ZTEST()
74 zassert_true(ret == 0, "Flash write failure (%d)", ret); in ZTEST()
76 ret = flash_area_flatten(ctx.flash_area, 0, ctx.flash_area->fa_size); in ZTEST()
77 zassert_true(ret == 0, "Flash erase failure (%d)", ret); in ZTEST()
[all …]
/Zephyr-latest/samples/boards/microchip/mec172xevb_assy6906/rom_api/src/
Dmain.c27 0x45, 0x73, 0x66, 0x72, 0x44, 0x36, 0x70, 0x73,
28 0x47, 0x7a, 0x66, 0x70, 0x78, 0x56, 0x78, 0x6b,
29 0x70, 0x65, 0x4a, 0x56, 0x55, 0x4a, 0x58, 0x62,
30 0x41, 0x61, 0x53, 0x33, 0x6e, 0x55, 0x78, 0x41,
31 0x46, 0x6d, 0x34, 0x77, 0x42,
34 0xe4, 0x70, 0xa9, 0x89, 0xc5, 0x37, 0xda, 0x0d,
35 0x9f, 0x55, 0x9a, 0x4e, 0x9d, 0xed, 0xaa, 0x75,
36 0xf8, 0xe0, 0x58, 0x0f, 0xc4, 0x2e, 0x0d, 0x23,
37 0x03, 0x7c, 0x0f, 0x18,
40 0xe2, 0x82, 0x23, 0xfb, 0x3f, 0x6a, 0x49, 0x17,
[all …]

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