Lines Matching +full:0 +full:x38
24 dram1_0_seg : org = 0x3FFC0000, len = 0x20000
25 dram0_0_seg : org = 0x3FFE0000, len = 0x20000
26 iram0_0_seg : org = 0x40000000, len = 0x178
27 iram0_1_seg : org = 0x40000178, len = 0x8
28 iram0_2_seg : org = 0x40000180, len = 0x38
29 iram0_3_seg : org = 0x400001B8, len = 0x8
30 iram0_4_seg : org = 0x400001C0, len = 0x38
31 iram0_5_seg : org = 0x400001F8, len = 0x8
32 iram0_6_seg : org = 0x40000200, len = 0x38
33 iram0_7_seg : org = 0x40000238, len = 0x8
34 iram0_8_seg : org = 0x40000240, len = 0x38
35 iram0_9_seg : org = 0x40000278, len = 0x8
36 iram0_10_seg : org = 0x40000280, len = 0x38
37 iram0_11_seg : org = 0x400002B8, len = 0x8
38 iram0_12_seg : org = 0x400002C0, len = 0x38
39 iram0_13_seg : org = 0x400002F8, len = 0x8
40 iram0_14_seg : org = 0x40000300, len = 0x38
41 iram0_15_seg : org = 0x40000338, len = 0x8
42 iram0_16_seg : org = 0x40000340, len = 0x38
43 iram0_17_seg : org = 0x40000378, len = 0x48
44 iram0_18_seg : org = 0x400003C0, len = 0x40
45 iram0_19_seg : org = 0x40000400, len = 0x1FC00
46 srom0_seg : org = 0x50000000, len = 0x300
47 srom1_seg : org = 0x50000300, len = 0xFFFD00
48 RAM : org = 0x60000000, len = 0x4000000
50 IDT_LIST : org = 0x3ffbe000, len = 0x2000
91 _memmap_mem_dram1_start = 0x3ffc0000;
92 _memmap_mem_dram1_end = 0x3ffe0000;
93 _memmap_mem_dram0_start = 0x3ffe0000;
94 _memmap_mem_dram0_end = 0x40000000;
95 _memmap_mem_iram0_start = 0x40000000;
96 _memmap_mem_iram0_end = 0x40020000;
97 _memmap_mem_srom_start = 0x50000000;
98 _memmap_mem_srom_end = 0x51000000;
99 _memmap_mem_sram_start = 0x60000000;
100 _memmap_mem_sram_end = 0x64000000;
103 _memmap_seg_dram1_0_start = 0x3ffc0000;
104 _memmap_seg_dram1_0_max = 0x3ffe0000;
105 _memmap_seg_dram0_0_start = 0x3ffe0000;
106 _memmap_seg_dram0_0_max = 0x40000000;
107 _memmap_seg_iram0_0_start = 0x40000000;
108 _memmap_seg_iram0_0_max = 0x40000178;
109 _memmap_seg_iram0_1_start = 0x40000178;
110 _memmap_seg_iram0_1_max = 0x40000180;
111 _memmap_seg_iram0_2_start = 0x40000180;
112 _memmap_seg_iram0_2_max = 0x400001b8;
113 _memmap_seg_iram0_3_start = 0x400001b8;
114 _memmap_seg_iram0_3_max = 0x400001c0;
115 _memmap_seg_iram0_4_start = 0x400001c0;
116 _memmap_seg_iram0_4_max = 0x400001f8;
117 _memmap_seg_iram0_5_start = 0x400001f8;
118 _memmap_seg_iram0_5_max = 0x40000200;
119 _memmap_seg_iram0_6_start = 0x40000200;
120 _memmap_seg_iram0_6_max = 0x40000238;
121 _memmap_seg_iram0_7_start = 0x40000238;
122 _memmap_seg_iram0_7_max = 0x40000240;
123 _memmap_seg_iram0_8_start = 0x40000240;
124 _memmap_seg_iram0_8_max = 0x40000278;
125 _memmap_seg_iram0_9_start = 0x40000278;
126 _memmap_seg_iram0_9_max = 0x40000280;
127 _memmap_seg_iram0_10_start = 0x40000280;
128 _memmap_seg_iram0_10_max = 0x400002b8;
129 _memmap_seg_iram0_11_start = 0x400002b8;
130 _memmap_seg_iram0_11_max = 0x400002c0;
131 _memmap_seg_iram0_12_start = 0x400002c0;
132 _memmap_seg_iram0_12_max = 0x400002f8;
133 _memmap_seg_iram0_13_start = 0x400002f8;
134 _memmap_seg_iram0_13_max = 0x40000300;
135 _memmap_seg_iram0_14_start = 0x40000300;
136 _memmap_seg_iram0_14_max = 0x40000338;
137 _memmap_seg_iram0_15_start = 0x40000338;
138 _memmap_seg_iram0_15_max = 0x40000340;
139 _memmap_seg_iram0_16_start = 0x40000340;
140 _memmap_seg_iram0_16_max = 0x40000378;
141 _memmap_seg_iram0_17_start = 0x40000378;
142 _memmap_seg_iram0_17_max = 0x400003c0;
143 _memmap_seg_iram0_18_start = 0x400003c0;
144 _memmap_seg_iram0_18_max = 0x40000400;
145 _memmap_seg_iram0_19_start = 0x40000400;
146 _memmap_seg_iram0_19_max = 0x40020000;
147 _memmap_seg_srom0_start = 0x50000000;
148 _memmap_seg_srom0_max = 0x50000300;
149 _memmap_seg_srom1_start = 0x50000300;
150 _memmap_seg_srom1_max = 0x51000000;
151 _memmap_seg_sram0_start = 0x60000000;
152 _memmap_seg_sram0_max = 0x64000000;
154 _rom_store_table = 0;
155 PROVIDE(_memmap_vecbase_reset = 0x40000000);
156 PROVIDE(_memmap_reset_vector = 0x50000000);
158 _memmap_cacheattr_wb_base = 0x00001110;
159 _memmap_cacheattr_wt_base = 0x00001110;
160 _memmap_cacheattr_bp_base = 0x00002220;
161 _memmap_cacheattr_unused_mask = 0xFFFF000F;
162 _memmap_cacheattr_wb_trapnull = 0x2222111F;
163 _memmap_cacheattr_wba_trapnull = 0x2222111F;
164 _memmap_cacheattr_wbna_trapnull = 0x2222111F;
165 _memmap_cacheattr_wt_trapnull = 0x2222111F;
166 _memmap_cacheattr_bp_trapnull = 0x2222222F;
167 _memmap_cacheattr_wb_strict = 0xFFFF111F;
168 _memmap_cacheattr_wt_strict = 0xFFFF111F;
169 _memmap_cacheattr_bp_strict = 0xFFFF222F;
170 _memmap_cacheattr_wb_allvalid = 0x22221112;
171 _memmap_cacheattr_wt_allvalid = 0x22221112;
172 _memmap_cacheattr_bp_allvalid = 0x22222222;
216 _memmap_seg_dram1_0_end = ALIGN(0x8);
247 _memmap_seg_dram0_0_end = ALIGN(0x8);
255 _memmap_seg_iram0_0_end = ALIGN(0x8);
263 _memmap_seg_iram0_1_end = ALIGN(0x8);
271 _memmap_seg_iram0_2_end = ALIGN(0x8);
279 _memmap_seg_iram0_3_end = ALIGN(0x8);
287 _memmap_seg_iram0_4_end = ALIGN(0x8);
295 _memmap_seg_iram0_5_end = ALIGN(0x8);
303 _memmap_seg_iram0_6_end = ALIGN(0x8);
311 _memmap_seg_iram0_7_end = ALIGN(0x8);
319 _memmap_seg_iram0_8_end = ALIGN(0x8);
327 _memmap_seg_iram0_9_end = ALIGN(0x8);
335 _memmap_seg_iram0_10_end = ALIGN(0x8);
343 _memmap_seg_iram0_11_end = ALIGN(0x8);
351 _memmap_seg_iram0_12_end = ALIGN(0x8);
359 _memmap_seg_iram0_13_end = ALIGN(0x8);
367 _memmap_seg_iram0_14_end = ALIGN(0x8);
375 _memmap_seg_iram0_15_end = ALIGN(0x8);
383 _memmap_seg_iram0_16_end = ALIGN(0x8);
391 _memmap_seg_iram0_17_end = ALIGN(0x8);
399 _memmap_seg_iram0_18_end = ALIGN(0x8);
407 _memmap_seg_iram0_19_end = ALIGN(0x8);
416 _memmap_seg_srom0_end = ALIGN(0x8);
435 _memmap_seg_srom1_end = ALIGN(0x8);
601 _end = ALIGN(0x8);
603 PROVIDE(end = ALIGN(0x8));
604 _stack_sentry = ALIGN(0x8);
605 _memmap_seg_sram0_end = ALIGN(0x8);
607 __stack = 0x64000000;
608 _heap_sentry = 0x64000000;
609 .comment 0 : { *(.comment) }
610 .debug 0 : { *(.debug) }
611 .line 0 : { *(.line) }
612 .debug_srcinfo 0 : { *(.debug_srcinfo) }
613 .debug_sfnames 0 : { *(.debug_sfnames) }
614 .debug_aranges 0 : { *(.debug_aranges) }
615 .debug_pubnames 0 : { *(.debug_pubnames) }
616 .debug_info 0 : { *(.debug_info) }
617 .debug_abbrev 0 : { *(.debug_abbrev) }
618 .debug_line 0 : { *(.debug_line) }
619 .debug_frame 0 : { *(.debug_frame) }
620 .debug_str 0 : { *(.debug_str) }
621 .debug_loc 0 : { *(.debug_loc) }
622 .debug_macinfo 0 : { *(.debug_macinfo) }
623 .debug_weaknames 0 : { *(.debug_weaknames) }
624 .debug_funcnames 0 : { *(.debug_funcnames) }
625 .debug_typenames 0 : { *(.debug_typenames) }
626 .debug_varnames 0 : { *(.debug_varnames) }
627 .debug_ranges 0 : { *(.debug_ranges) }
628 .debug_addr 0 : { *(.debug_addr) }
629 .debug_line_str 0 : { *(.debug_line_str) }
630 .debug_loclists 0 : { *(.debug_loclists) }
631 .debug_macro 0 : { *(.debug_macro) }
632 .debug_names 0 : { *(.debug_names) }
633 .debug_rnglists 0 : { *(.debug_rnglists) }
634 .debug_str_offsets 0 : { *(.debug_str_offsets) }
635 .debug_sup 0 : { *(.debug_sup) }
636 .xtensa.info 0 : { *(.xtensa.info) }
637 .xt.insn 0 :
642 .xt.prop 0 :
648 .xt.lit 0 :
654 .debug.xt.callgraph 0 :