1 /* 2 * Copyright (c) 2022 Badgerd Technologies B.V. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Driver is developed to be used with Zephyr. And it only supports i2c interface. 7 * 8 * Author: Talha Can Havadar <havadartalha@gmail.com> 9 * 10 */ 11 12 #ifndef ZEPHYR_DRIVERS_SENSOR_BMP581_BMP581_H_ 13 #define ZEPHYR_DRIVERS_SENSOR_BMP581_BMP581_H_ 14 15 #include <zephyr/device.h> 16 #include <zephyr/drivers/gpio.h> 17 #include <zephyr/drivers/i2c.h> 18 #include <zephyr/drivers/sensor.h> 19 #include <zephyr/sys/util.h> 20 #include <zephyr/types.h> 21 #include <zephyr/drivers/sensor/bmp581_user.h> 22 23 #define DT_DRV_COMPAT bosch_bmp581 24 25 /* UTILITY MACROS */ 26 #define BMP5_SET_LOW_BYTE 0x00FFu 27 #define BMP5_SET_HIGH_BYTE 0xFF00u 28 29 /* BIT SLICE GET AND SET FUNCTIONS */ 30 #define BMP5_GET_BITSLICE(regvar, bitname) ((regvar & bitname##_MSK) >> bitname##_POS) 31 32 #define BMP5_SET_BITSLICE(regvar, bitname, val) \ 33 ((regvar & ~bitname##_MSK) | ((val << bitname##_POS) & bitname##_MSK)) 34 35 #define BMP5_GET_LSB(var) (uint8_t)(var & BMP5_SET_LOW_BYTE) 36 #define BMP5_GET_MSB(var) (uint8_t)((var & BMP5_SET_HIGH_BYTE) >> 8) 37 38 #define BMP5_SET_BIT_VAL_0(reg_data, bitname) (reg_data & ~(bitname##_MSK)) 39 40 #define BMP5_SET_BITS_POS_0(reg_data, bitname, data) \ 41 ((reg_data & ~(bitname##_MSK)) | (data & bitname##_MSK)) 42 43 #define BMP5_GET_BITS_POS_0(reg_data, bitname) (reg_data & (bitname##_MSK)) 44 45 #define BMP5_OK 0 46 #define BMP5_ENABLE 1u 47 #define BMP5_DISABLE 0u 48 49 /* BMP5 Registers */ 50 #define BMP5_REG_CHIP_ID 0x01 51 #define BMP5_REG_REV_ID 0x02 52 #define BMP5_REG_CHIP_STATUS 0x11 53 #define BMP5_REG_DRIVE_CONFIG 0x13 54 #define BMP5_REG_INT_CONFIG 0x14 55 #define BMP5_REG_INT_SOURCE 0x15 56 #define BMP5_REG_FIFO_CONFIG 0x16 57 #define BMP5_REG_FIFO_COUNT 0x17 58 #define BMP5_REG_FIFO_SEL 0x18 59 #define BMP5_REG_TEMP_DATA_XLSB 0x1D 60 #define BMP5_REG_TEMP_DATA_LSB 0x1E 61 #define BMP5_REG_TEMP_DATA_MSB 0x1F 62 #define BMP5_REG_PRESS_DATA_XLSB 0x20 63 #define BMP5_REG_PRESS_DATA_LSB 0x21 64 #define BMP5_REG_PRESS_DATA_MSB 0x22 65 #define BMP5_REG_INT_STATUS 0x27 66 #define BMP5_REG_STATUS 0x28 67 #define BMP5_REG_FIFO_DATA 0x29 68 #define BMP5_REG_NVM_ADDR 0x2B 69 #define BMP5_REG_NVM_DATA_LSB 0x2C 70 #define BMP5_REG_NVM_DATA_MSB 0x2D 71 #define BMP5_REG_DSP_CONFIG 0x30 72 #define BMP5_REG_DSP_IIR 0x31 73 #define BMP5_REG_OOR_THR_P_LSB 0x32 74 #define BMP5_REG_OOR_THR_P_MSB 0x33 75 #define BMP5_REG_OOR_RANGE 0x34 76 #define BMP5_REG_OOR_CONFIG 0x35 77 #define BMP5_REG_OSR_CONFIG 0x36 78 #define BMP5_REG_ODR_CONFIG 0x37 79 #define BMP5_REG_OSR_EFF 0x38 80 #define BMP5_REG_CMD 0x7E 81 /* endof BMP5 Registers */ 82 83 /* Chip id of BMP5 */ 84 #define BMP5_CHIP_ID_PRIM 0x50 85 #define BMP5_CHIP_ID_SEC 0x51 86 87 /* I2C addresses */ 88 #define BMP5_I2C_ADDR_PRIM 0x46 89 #define BMP5_I2C_ADDR_SEC 0x47 90 91 /* NVM addresses */ 92 #define BMP5_NVM_START_ADDR 0x20 93 #define BMP5_NVM_END_ADDR 0x22 94 95 /* Interface settings */ 96 #define BMP5_SPI_RD_MASK 0x80 97 98 /* Delay definition */ 99 #define BMP5_DELAY_US_SOFT_RESET 2000 100 #define BMP5_DELAY_US_STANDBY 2500 101 #define BMP5_DELAY_US_NVM_READY_READ 800 102 #define BMP5_DELAY_US_NVM_READY_WRITE 10000 103 104 /* Soft reset command */ 105 #define BMP5_SOFT_RESET_CMD 0xB6 106 107 /*! NVM command */ 108 #define BMP5_NVM_FIRST_CMND 0x5D 109 #define BMP5_NVM_READ_ENABLE_CMND 0xA5 110 #define BMP5_NVM_WRITE_ENABLE_CMND 0xA0 111 112 /* Deepstandby enable/disable */ 113 #define BMP5_DEEP_ENABLED 0 114 #define BMP5_DEEP_DISABLED 1 115 116 /*! Fifo frame configuration */ 117 #define BMP5_FIFO_EMPTY 0X7F 118 #define BMP5_FIFO_MAX_THRESHOLD_P_T_MODE 0x0F 119 #define BMP5_FIFO_MAX_THRESHOLD_P_MODE 0x1F 120 121 /* Macro is used to bypass both iir_t and iir_p together */ 122 #define BMP5_IIR_BYPASS 0xC0 123 124 /* Pressure Out-of-range count limit */ 125 #define BMP5_OOR_COUNT_LIMIT_1 0x00 126 #define BMP5_OOR_COUNT_LIMIT_3 0x01 127 #define BMP5_OOR_COUNT_LIMIT_7 0x02 128 #define BMP5_OOR_COUNT_LIMIT_15 0x03 129 130 /* Interrupt configurations */ 131 #define BMP5_INT_MODE_PULSED 0 132 #define BMP5_INT_MODE_LATCHED 1 133 134 #define BMP5_INT_POL_ACTIVE_LOW 0 135 #define BMP5_INT_POL_ACTIVE_HIGH 1 136 137 #define BMP5_INT_OD_PUSHPULL 0 138 #define BMP5_INT_OD_OPENDRAIN 1 139 140 /* NVM and Interrupt status asserted macros */ 141 #define BMP5_INT_ASSERTED_DRDY 0x01 142 #define BMP5_INT_ASSERTED_FIFO_FULL 0x02 143 #define BMP5_INT_ASSERTED_FIFO_THRES 0x04 144 #define BMP5_INT_ASSERTED_PRESSURE_OOR 0x08 145 #define BMP5_INT_ASSERTED_POR_SOFTRESET_COMPLETE 0x10 146 #define BMP5_INT_NVM_RDY 0x02 147 #define BMP5_INT_NVM_ERR 0x04 148 #define BMP5_INT_NVM_CMD_ERR 0x08 149 150 /* Interrupt configurations */ 151 #define BMP5_INT_MODE_MSK 0x01 152 153 #define BMP5_INT_POL_MSK 0x02 154 #define BMP5_INT_POL_POS 1 155 156 #define BMP5_INT_OD_MSK 0x04 157 #define BMP5_INT_OD_POS 2 158 159 #define BMP5_INT_EN_MSK 0x08 160 #define BMP5_INT_EN_POS 3 161 162 #define BMP5_INT_DRDY_EN_MSK 0x01 163 164 #define BMP5_INT_FIFO_FULL_EN_MSK 0x02 165 #define BMP5_INT_FIFO_FULL_EN_POS 1 166 167 #define BMP5_INT_FIFO_THRES_EN_MSK 0x04 168 #define BMP5_INT_FIFO_THRES_EN_POS 2 169 170 #define BMP5_INT_OOR_PRESS_EN_MSK 0x08 171 #define BMP5_INT_OOR_PRESS_EN_POS 3 172 173 /* ODR configuration */ 174 #define BMP5_ODR_MSK 0x7C 175 #define BMP5_ODR_POS 2 176 177 /* OSR configurations */ 178 #define BMP5_TEMP_OS_MSK 0x07 179 180 #define BMP5_PRESS_OS_MSK 0x38 181 #define BMP5_PRESS_OS_POS 3 182 183 /* Pressure enable */ 184 #define BMP5_PRESS_EN_MSK 0x40 185 #define BMP5_PRESS_EN_POS 6 186 187 /* IIR configurations */ 188 #define BMP5_SET_IIR_TEMP_MSK 0x07 189 190 #define BMP5_SET_IIR_PRESS_MSK 0x38 191 #define BMP5_SET_IIR_PRESS_POS 3 192 193 #define BMP5_OOR_SEL_IIR_PRESS_MSK 0x80 194 #define BMP5_OOR_SEL_IIR_PRESS_POS 7 195 196 #define BMP5_SHDW_SET_IIR_TEMP_MSK 0x08 197 #define BMP5_SHDW_SET_IIR_TEMP_POS 3 198 199 #define BMP5_SHDW_SET_IIR_PRESS_MSK 0x20 200 #define BMP5_SHDW_SET_IIR_PRESS_POS 5 201 202 #define BMP5_SET_FIFO_IIR_TEMP_MSK 0x10 203 #define BMP5_SET_FIFO_IIR_TEMP_POS 4 204 205 #define BMP5_SET_FIFO_IIR_PRESS_MSK 0x40 206 #define BMP5_SET_FIFO_IIR_PRESS_POS 6 207 208 #define BMP5_IIR_FLUSH_FORCED_EN_MSK 0x04 209 #define BMP5_IIR_FLUSH_FORCED_EN_POS 2 210 211 /* Effective OSR configurations and ODR valid status */ 212 #define BMP5_OSR_TEMP_EFF_MSK 0x07 213 214 #define BMP5_OSR_PRESS_EFF_MSK 0x38 215 #define BMP5_OSR_PRESS_EFF_POS 3 216 217 #define BMP5_ODR_IS_VALID_MSK 0x80 218 #define BMP5_ODR_IS_VALID_POS 7 219 220 /* Powermode */ 221 #define BMP5_POWERMODE_MSK 0x03 222 223 #define BMP5_DEEP_DISABLE_MSK 0x80 224 #define BMP5_DEEP_DISABLE_POS 7 225 226 /* Fifo configurations */ 227 #define BMP5_FIFO_THRESHOLD_MSK 0x1F 228 229 #define BMP5_FIFO_MODE_MSK 0x20 230 #define BMP5_FIFO_MODE_POS 5 231 232 #define BMP5_FIFO_DEC_SEL_MSK 0x1C 233 #define BMP5_FIFO_DEC_SEL_POS 2 234 235 #define BMP5_FIFO_COUNT_MSK 0x3F 236 237 #define BMP5_FIFO_FRAME_SEL_MSK 0x03 238 239 /* Out-of-range configuration */ 240 #define BMP5_OOR_THR_P_LSB_MSK 0x0000FF 241 242 #define BMP5_OOR_THR_P_MSB_MSK 0x00FF00 243 244 #define BMP5_OOR_THR_P_XMSB_MSK 0x010000 245 #define BMP5_OOR_THR_P_XMSB_POS 16 246 247 /* Macro to mask xmsb value of oor threshold from register(0x35) value */ 248 #define BMP5_OOR_THR_P_XMSB_REG_MSK 0x01 249 250 #define BMP5_OOR_COUNT_LIMIT_MSK 0xC0 251 #define BMP5_OOR_COUNT_LIMIT_POS 6 252 253 /* NVM configuration */ 254 #define BMP5_NVM_ADDR_MSK 0x3F 255 256 #define BMP5_NVM_PROG_EN_MSK 0x40 257 #define BMP5_NVM_PROG_EN_POS 6 258 259 #define BMP5_NVM_DATA_LSB_MSK 0x00FF 260 261 #define BMP5_NVM_DATA_MSB_MSK 0xFF00 262 263 /*! 264 * @brief OSR, ODR and pressure configuration structure 265 */ 266 struct bmp581_osr_odr_press_config { 267 /*! Temperature oversampling 268 * Assignable macros : 269 * - BMP5_OVERSAMPLING_1X 270 * - BMP5_OVERSAMPLING_2X 271 * - BMP5_OVERSAMPLING_4X 272 * - BMP5_OVERSAMPLING_8X 273 * - BMP5_OVERSAMPLING_16X 274 * - BMP5_OVERSAMPLING_32X 275 * - BMP5_OVERSAMPLING_64X 276 * - BMP5_OVERSAMPLING_128X 277 */ 278 uint8_t osr_t; 279 280 /*! Pressure oversampling 281 * Assignable macros : 282 * - BMP5_OVERSAMPLING_1X 283 * - BMP5_OVERSAMPLING_2X 284 * - BMP5_OVERSAMPLING_4X 285 * - BMP5_OVERSAMPLING_8X 286 * - BMP5_OVERSAMPLING_16X 287 * - BMP5_OVERSAMPLING_32X 288 * - BMP5_OVERSAMPLING_64X 289 * - BMP5_OVERSAMPLING_128X 290 */ 291 uint8_t osr_p; 292 293 /*! Enable pressure 294 * BMP5_ENABLE = Enables pressure data 295 * BMP5_DISABLE = Disables pressure data 296 */ 297 uint8_t press_en; 298 299 /*! Output Data Rate */ 300 uint8_t odr; 301 }; 302 303 struct bmp581_sample { 304 struct sensor_value pressure; 305 struct sensor_value temperature; 306 }; 307 308 struct bmp581_data { 309 uint8_t chip_id; 310 struct bmp581_sample last_sample; 311 struct bmp581_osr_odr_press_config osr_odr_press_config; 312 }; 313 314 struct bmp581_config { 315 struct i2c_dt_spec i2c; 316 }; 317 318 #endif /* ZEPHYR_DRIVERS_SENSOR_BMP581_BMP581_H_ */ 319
