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12

/Zephyr-latest/samples/drivers/fpga/fpga_controller/src/
Dredled.h9 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
10 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
11 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
12 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
13 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
14 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
15 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
16 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
17 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
18 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
[all …]
Dgreenled.h9 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
10 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
11 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
12 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
13 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
14 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
15 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
16 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
17 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
18 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dnumaker_m2l31x_clock.h10 #define NUMAKER_CLK_CLKSEL0_HCLKSEL_HXT 0x00000000
11 #define NUMAKER_CLK_CLKSEL0_HCLKSEL_LXT 0x00000001
12 #define NUMAKER_CLK_CLKSEL0_HCLKSEL_PLL 0x00000002
13 #define NUMAKER_CLK_CLKSEL0_HCLKSEL_LIRC 0x00000003
14 #define NUMAKER_CLK_CLKSEL0_HCLKSEL_MIRC 0x00000005
15 #define NUMAKER_CLK_CLKSEL0_HCLKSEL_HIRC48M 0x00000006
16 #define NUMAKER_CLK_CLKSEL0_HCLKSEL_HIRC 0x00000007
17 #define NUMAKER_CLK_CLKSEL0_HCLK0SEL_HXT 0x00000000
18 #define NUMAKER_CLK_CLKSEL0_HCLK0SEL_LXT 0x00000001
19 #define NUMAKER_CLK_CLKSEL0_HCLK0SEL_PLL 0x00000002
[all …]
/Zephyr-latest/subsys/bluetooth/host/classic/
Dhfp_internal.h15 #define BT_HFP_AG_FEATURE_3WAY_CALL 0x00000001 /* Three-way calling */
16 #define BT_HFP_AG_FEATURE_ECNR 0x00000002 /* EC and/or NR function */
17 #define BT_HFP_AG_FEATURE_VOICE_RECG 0x00000004 /* Voice recognition */
18 #define BT_HFP_AG_FEATURE_INBAND_RINGTONE 0x00000008 /* In-band ring capability */
19 #define BT_HFP_AG_FEATURE_VOICE_TAG 0x00000010 /* Attach no. to voice tag */
20 #define BT_HFP_AG_FEATURE_REJECT_CALL 0x00000020 /* Ability to reject call */
21 #define BT_HFP_AG_FEATURE_ECS 0x00000040 /* Enhanced call status */
22 #define BT_HFP_AG_FEATURE_ECC 0x00000080 /* Enhanced call control */
23 #define BT_HFP_AG_FEATURE_EXT_ERR 0x00000100 /* Extended error codes */
24 #define BT_HFP_AG_FEATURE_CODEC_NEG 0x00000200 /* Codec negotiation */
[all …]
/Zephyr-latest/dts/bindings/clock/
Dst,stm32wba-rcc.yaml34 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
47 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>,
Dst,stm32-rcc.yaml33 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
49 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>,
/Zephyr-latest/drivers/sensor/st/vl53l1x/
Dvl53l1_platform_log.h64 #define VL53L1_TRACE_LEVEL_NONE 0x00000000
65 #define VL53L1_TRACE_LEVEL_ERRORS 0x00000001
66 #define VL53L1_TRACE_LEVEL_WARNING 0x00000002
67 #define VL53L1_TRACE_LEVEL_INFO 0x00000004
68 #define VL53L1_TRACE_LEVEL_DEBUG 0x00000008
69 #define VL53L1_TRACE_LEVEL_ALL 0x00000010
70 #define VL53L1_TRACE_LEVEL_IGNORE 0x00000020
72 #define VL53L1_TRACE_FUNCTION_NONE 0x00000000
73 #define VL53L1_TRACE_FUNCTION_I2C 0x00000001
74 #define VL53L1_TRACE_FUNCTION_ALL 0x7fffffff
[all …]
/Zephyr-latest/drivers/ethernet/
Deth_lan9250_priv.h23 #define LAN9250_SPI_INSTR_WRITE 0x02
24 #define LAN9250_SPI_INSTR_READ 0x03
27 #define LAN9250_TX_CMD_A_INT_ON_COMP 0x80000000
28 #define LAN9250_TX_CMD_A_BUFFER_ALIGN_4B 0x00000000
29 #define LAN9250_TX_CMD_A_START_OFFSET_0B 0x00000000
30 #define LAN9250_TX_CMD_A_FIRST_SEG 0x00002000
31 #define LAN9250_TX_CMD_A_LAST_SEG 0x00001000
34 #define LAN9250_TX_CMD_B_PACKET_TAG 0xFFFF0000
37 #define LAN9250_RX_STS_PACKET_LEN 0x3FFF0000
40 #define LAN9250_RX_DATA_FIFO 0x0000
[all …]
Deth_xlnx_gem_priv.h30 * [31 .. 02] Mask for effective buffer address -> excludes [1..0]
34 #define ETH_XLNX_GEM_RXBD_WRAP_BIT 0x00000002
35 #define ETH_XLNX_GEM_RXBD_USED_BIT 0x00000001
36 #define ETH_XLNX_GEM_RXBD_BUFFER_ADDR_MASK 0xFFFFFFFC
49 * [21] VLAN tag (type ID 0x8100) detected
50 * [20] Priority tag: VLAN tag (type ID 0x8100) and null VLAN identifier
59 #define ETH_XLNX_GEM_RXBD_BCAST_BIT 0x80000000
60 #define ETH_XLNX_GEM_RXBD_MCAST_HASH_MATCH_BIT 0x40000000
61 #define ETH_XLNX_GEM_RXBD_UCAST_HASH_MATCH_BIT 0x20000000
62 #define ETH_XLNX_GEM_RXBD_SPEC_ADDR_MATCH_BIT 0x08000000
[all …]
Deth_cyclonev_priv.h8 * 3504-0 Universal 10/100/1000 Ethernet MAC (DWC_gmac)
57 #define RSTMGR_BASE 0xffd05000
62 #define RSTMGR_PERMODRST_OFST 0x14
64 #define RSTMGR_PERMODRST_ADDR 0xFFD05014
66 #define RSTMGR_PERMODRST_EMAC0_SET_MSK 0x00000001
68 #define RSTMGR_PERMODRST_EMAC1_SET_MSK 0x00000002
73 #define SYSMGR_BASE 0xffd08000
74 #define SYSMGR_EMAC_ADDR 0xffd08060
75 #define SYSMGR_FPGAINTF_INDIV_ADDR 0xffd08004
80 #define SYSMGR_EMAC_OFST 0x60
[all …]
/Zephyr-latest/drivers/fpga/
Dfpga_eos_s3.h13 /* Fabric Configuration Control Register, offset: 0x000 */
15 /* Maximum Bit Length Count, offset: 0x004 */
17 /* Maximum Word Length Count, offset: 0x008 */
20 /* Configuration Data, offset: 0xFFC */
26 #define FB_CFG_ENABLE ((uint32_t)(0x00000200))
27 #define FB_CFG_DISABLE ((uint32_t)(0x00000000))
29 #define CFG_CTL_APB_CFG_WR ((uint32_t)(0x00008000))
30 #define CFG_CTL_APB_CFG_RD ((uint32_t)(0x00004000))
31 #define CFG_CTL_APB_WL_DIN ((uint32_t)(0x00003C00))
32 #define CFG_CTL_APB_PARTIAL_LOAD ((uint32_t)(0x00000200))
[all …]
/Zephyr-latest/include/zephyr/arch/riscv/
Dcsr.h12 #define MSTATUS_UIE 0x00000001
13 #define MSTATUS_SIE 0x00000002
14 #define MSTATUS_HIE 0x00000004
15 #define MSTATUS_MIE 0x00000008
16 #define MSTATUS_UPIE 0x00000010
17 #define MSTATUS_SPIE 0x00000020
18 #define MSTATUS_HPIE 0x00000040
19 #define MSTATUS_MPIE 0x00000080
20 #define MSTATUS_SPP 0x00000100
21 #define MSTATUS_HPP 0x00000600
[all …]
/Zephyr-latest/include/zephyr/drivers/timer/
Dti_dmtimer.h12 #define TI_DM_TIMER_TIDR (0x00)
13 #define TI_DM_TIMER_TIOCP_CFG (0x10)
14 #define TI_DM_TIMER_IRQ_EOI (0x20)
15 #define TI_DM_TIMER_IRQSTATUS_RAW (0x24)
16 #define TI_DM_TIMER_IRQSTATUS (0x28) /* Interrupt status register */
17 #define TI_DM_TIMER_IRQENABLE_SET (0x2c) /* Interrupt enable register */
18 #define TI_DM_TIMER_IRQENABLE_CLR (0x30) /* Interrupt disable register */
19 #define TI_DM_TIMER_IRQWAKEEN (0x34)
20 #define TI_DM_TIMER_TCLR (0x38) /* Control register */
21 #define TI_DM_TIMER_TCRR (0x3c) /* Counter register */
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dcc13xx_cc26xx-pinctrl.h13 #define IOC_PORT_GPIO 0x00000000 /* Default general purpose IO usage */
14 #define IOC_PORT_AON_CLK32K 0x00000007 /* AON External 32kHz clock */
15 #define IOC_PORT_AUX_IO 0x00000008 /* AUX IO Pin */
16 #define IOC_PORT_MCU_SSI0_RX 0x00000009 /* MCU SSI0 Receive Pin */
17 #define IOC_PORT_MCU_SSI0_TX 0x0000000A /* MCU SSI0 Transmit Pin */
18 #define IOC_PORT_MCU_SSI0_FSS 0x0000000B /* MCU SSI0 FSS Pin */
19 #define IOC_PORT_MCU_SSI0_CLK 0x0000000C /* MCU SSI0 Clock Pin */
20 #define IOC_PORT_MCU_I2C_MSSDA 0x0000000D /* MCU I2C Data Pin */
21 #define IOC_PORT_MCU_I2C_MSSCL 0x0000000E /* MCU I2C Clock Pin */
22 #define IOC_PORT_MCU_UART0_RX 0x0000000F /* MCU UART0 Receive Pin */
[all …]
/Zephyr-latest/tests/lib/cmsis_dsp/filtering/src/
Ddecim_q31.pat2 0xA3CB5D0F, 0x80000000, 0xF6C534E5, 0x1C4CEDDB,
3 0x7FFFFFFF, 0x0EC8F275, 0x6B76F394, 0xCBDFAEB1,
4 0x7FFFFFFF, 0x80000000, 0x635590E9, 0xEBA995F0,
5 0x6C13AF1C, 0xE6D92890, 0x7FFFFFFF, 0xE57502C1,
6 0x7FFFFFFF, 0xA9F6FB47, 0x7FFFFFFF, 0x98464279,
7 0x6EFC640D, 0xD1378287, 0x606B883A, 0x488C89D2,
8 0xCED2A4A4, 0x30D44367, 0x80000000, 0x96074C58,
9 0x5BF5A0C5, 0x319DF592, 0xA4776275, 0xAFE65AC6,
10 0x2FAB2151, 0xAED7C4F1, 0x7FFFFFFF, 0xB884209B,
11 0x04FC52FD, 0x37C26698, 0x0806F6CB, 0x4EC01ED6,
[all …]
Ddecim_f32.pat2 0x3d9aeafc, 0x3f800000, 0xbf1bcebc, 0x3d288e27,
3 0xbf800000, 0xbe63a3ff, 0xbe6f74f1, 0x3f800000,
4 0x3f002294, 0xbf800000, 0x3f40d559, 0x3d7a1587,
5 0xbf800000, 0xbe538644, 0x3e3bd6b3, 0xbf4b0178,
6 0x3f800000, 0x3f3d911e, 0x3d8caa90, 0x3e705d9e,
7 0x3f800000, 0x3e0724d1, 0xbca52a4b, 0xbf065f5f,
8 0x3f1c89fb, 0x3efe135f, 0x3e162b52, 0xbe927bd0,
9 0x3f800000, 0x3f1271bb, 0x3f3ba3cc, 0x3f098db1,
10 0x3e064429, 0xbf40bd64, 0x3f66ad5b, 0xbe7961df,
11 0x3e74de85, 0xbf0400c9, 0xbf2c4e2d, 0xbf061416,
[all …]
Ddecim_q15.pat2 0x622A, 0xA3B0, 0x7FFF, 0xEE6A, 0x0017, 0x1920, 0x2D7A, 0x0668,
3 0x55AA, 0x7FFF, 0x0EF3, 0xE9A6, 0x0D34, 0x0416, 0x3691, 0x5F63,
4 0x8646, 0x216F, 0x7FFF, 0x1F5D, 0xFBE8, 0xF12F, 0xDC75, 0x01D3,
5 0x145C, 0x8000, 0xCF37, 0x2073, 0xFF9A, 0x160B, 0x8D76, 0xEB7A,
6 0x7FFF, 0x7AFF, 0xE957, 0x496F, 0xF15D, 0xFA99, 0x7FFF, 0x22A7,
7 0x531C, 0xB223, 0x709E, 0x4720, 0xF876, 0x8000, 0x5020, 0x7D7B,
8 0x5123, 0x527B, 0x981F, 0x61AB, 0x7EBF, 0xEDAE, 0x27C1, 0xF1EA,
9 0x1250, 0xCF0A, 0x4889, 0x7690, 0xDB17, 0x1B36, 0xD96D, 0xA59C,
10 0x879E, 0x7FFF, 0x5819, 0xDAF5, 0xE4E6, 0x0CCD, 0xCAF5, 0xD122,
11 0xD425, 0x2487, 0xD2DB, 0xFEA9, 0x7FFF, 0x2D33, 0xF585, 0xE92A,
[all …]
/Zephyr-latest/drivers/serial/
Duart_stellaris.c41 uint8_t _res1[0x010];
43 uint8_t _res2[0x04];
54 uint8_t _res3[0xf8c];
90 #define UARTFR_BUSY 0x00000008
91 #define UARTFR_RXFE 0x00000010
92 #define UARTFR_TXFF 0x00000020
93 #define UARTFR_RXFF 0x00000040
94 #define UARTFR_TXFE 0x00000080
96 #define UARTLCRH_FEN 0x00000010
97 #define UARTLCRH_WLEN 0x00000060
[all …]
/Zephyr-latest/tests/subsys/portability/cmsis_rtos_v2/src/
Dthread_flags.c15 #define FLAG1 (0x00000020)
16 #define FLAG2 (0x00000004)
18 #define ISR_FLAG (0x50)
28 flags = osThreadFlagsWait(FLAG1, osFlagsWaitAny | osFlagsNoClear, 0); in thread1()
58 zassert_equal(osThreadFlagsSet(NULL, 0), osFlagsErrorParameter, in thread2()
60 zassert_equal(osThreadFlagsSet(osThreadGetId(), 0x80010000), in thread2()
64 zassert_equal(osThreadFlagsClear(0x80010000), osFlagsErrorParameter, in thread2()
68 zassert_equal(osThreadFlagsWait(0x80010000, osFlagsWaitAny, 0), in thread2()
Devent_flags.c15 #define FLAG1 (0x00000020)
16 #define FLAG2 (0x00000004)
18 #define ISR_FLAG 0x50
43 zassert_equal(flags & FLAG2, 0, ""); in thread2()
64 .attr_bits = 0,
66 .cb_size = 0,
97 osFlagsWaitAny | osFlagsNoClear, 0); in test_event_flags_no_wait_timeout()
107 zassert_true(flags == 0U, in test_event_flags_no_wait_timeout()
150 zassert_equal(osEventFlagsSet(NULL, 0), osFlagsErrorParameter, in test_event_flags_signalled()
152 zassert_equal(osEventFlagsSet(evt_id, 0x80010000), in test_event_flags_signalled()
[all …]
/Zephyr-latest/tests/subsys/portability/cmsis_rtos_v1/src/
Dsignal.c15 #define SIGNAL1 (0x00000020)
16 #define SIGNAL2 (0x00000004)
19 #define SIGNAL_FLAG 0x00000001
20 #define ISR_SIGNAL 0x50
29 zassert_not_equal(signals, 0x80000000, ""); in Thread_1()
36 zassert_not_equal(signals, 0x80000000, ""); in Thread_2()
44 for (sig_cnt = 0; sig_cnt < max_signal_cnt; sig_cnt++) { in test_multiple_signal_flags()
49 zassert_not_equal(signals, 0x80000000, in test_multiple_signal_flags()
54 zassert_not_equal(signals, 0x80000000, ""); in test_multiple_signal_flags()
58 zassert_not_equal(signals, 0x80000000, in test_multiple_signal_flags()
[all …]
/Zephyr-latest/samples/boards/quicklogic/qomu/src/
Dusb2serial_bit.c10 0x00002808, 0x00000468, 0x00004452, 0x00009014, 0x00004924,
11 0x00000a29, 0x0000800a, 0x00001012, 0x00005514, 0x00004385,
12 0x00000289, 0x0000c82a, 0x00008402, 0x00000104, 0x000003c5,
13 0x000002b1, 0x00008002, 0x0000840a, 0x00001550, 0x00001301,
14 0x000002a5, 0x00000068, 0x00000408, 0x00000452, 0x00009804,
15 0x00000024, 0x0000ab29, 0x0000008a, 0x00003112, 0x00005454,
16 0x00000285, 0x00000301, 0x00008882, 0x00008562, 0x00004004,
17 0x000052c5, 0x00000b31, 0x00000822, 0x0000a54a, 0x00001410,
18 0x000002c1, 0x00000bb5, 0x00000828, 0x00000440, 0x00001442,
19 0x68284000, 0x24482000, 0x94d21000, 0x50140000, 0x09640000,
[all …]
/Zephyr-latest/include/zephyr/net/
Dwebsocket.h30 * @version 0.1.0
36 #define WEBSOCKET_FLAG_FINAL 0x00000001 /**< Final frame */
37 #define WEBSOCKET_FLAG_TEXT 0x00000002 /**< Textual data */
38 #define WEBSOCKET_FLAG_BINARY 0x00000004 /**< Binary data */
39 #define WEBSOCKET_FLAG_CLOSE 0x00000008 /**< Closing connection */
40 #define WEBSOCKET_FLAG_PING 0x00000010 /**< Ping message */
41 #define WEBSOCKET_FLAG_PONG 0x00000020 /**< Pong message */
45 WEBSOCKET_OPCODE_CONTINUE = 0x00, /**< Message continues */
46 WEBSOCKET_OPCODE_DATA_TEXT = 0x01, /**< Textual data */
47 WEBSOCKET_OPCODE_DATA_BINARY = 0x02, /**< Binary data */
[all …]
/Zephyr-latest/include/zephyr/arch/nios2/
Dnios2.h69 __asm__("mov %0, et" : "=r" (et)); in _nios2_read_et()
82 __asm__("mov %0, sp" : "=r" (sp)); in _nios2_read_sp()
104 __asm__ volatile ("flushda (%0)" :: "r" (addr)); in _nios2_dcache_addr_flush()
109 __asm__ volatile ("flushd (%0)" :: "r" (offset)); in z_nios2_dcache_flush()
114 __asm__ volatile ("flushi %0" :: "r" (offset)); in z_nios2_icache_flush()
127 NIOS2_CR_STATUS = 0,
147 * we get errors "Control register number must be in range 0-31 for
201 #define NIOS2_STATUS_PIE_MSK (0x00000001)
202 #define NIOS2_STATUS_PIE_OFST (0)
203 #define NIOS2_STATUS_U_MSK (0x00000002)
[all …]
/Zephyr-latest/drivers/ethernet/dwc_xgmac/
Deth_dwc_xgmac_priv.h19 #define RESET_BIT 0
25 #define XGMAC_CORE_BASE_ADDR_OFFSET (0x0000u)
26 #define XGMAC_MTL_BASE_ADDR_OFFSET (0x1000u)
27 #define XGMAC_MTL_TCQ_BASE_ADDR_OFFSET (0x1100u)
28 #define XGMAC_DMA_BASE_ADDR_OFFSET (0x3000u)
29 #define XGMAC_DMA_CHNL_BASE_ADDR_OFFSET (0x3100u)
30 #define XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(x) (XGMAC_DMA_CHNL_BASE_ADDR_OFFSET + (x * 0x80u))
31 #define XGMAC_MTL_TCQx_BASE_ADDR_OFFSET(x) (XGMAC_MTL_TCQ_BASE_ADDR_OFFSET + (x * 0x80u))
32 #define XGMAC_CORE_ADDRx_HIGH(x) (CORE_MAC_ADDRESS0_HIGH_OFST + (x) * 0x8)
33 #define XGMAC_CORE_ADDRx_LOW(x) (CORE_MAC_ADDRESS0_LOW_OFST + (x) * 0x8)
[all …]

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