Lines Matching +full:0 +full:x00000020
69 __asm__("mov %0, et" : "=r" (et)); in _nios2_read_et()
82 __asm__("mov %0, sp" : "=r" (sp)); in _nios2_read_sp()
104 __asm__ volatile ("flushda (%0)" :: "r" (addr)); in _nios2_dcache_addr_flush()
109 __asm__ volatile ("flushd (%0)" :: "r" (offset)); in z_nios2_dcache_flush()
114 __asm__ volatile ("flushi %0" :: "r" (offset)); in z_nios2_icache_flush()
127 NIOS2_CR_STATUS = 0,
147 * we get errors "Control register number must be in range 0-31 for
201 #define NIOS2_STATUS_PIE_MSK (0x00000001)
202 #define NIOS2_STATUS_PIE_OFST (0)
203 #define NIOS2_STATUS_U_MSK (0x00000002)
205 #define NIOS2_STATUS_EH_MSK (0x00000004)
207 #define NIOS2_STATUS_IH_MSK (0x00000008)
209 #define NIOS2_STATUS_IL_MSK (0x000003f0)
211 #define NIOS2_STATUS_CRS_MSK (0x0000fc00)
213 #define NIOS2_STATUS_PRS_MSK (0x003f0000)
215 #define NIOS2_STATUS_NMI_MSK (0x00400000)
217 #define NIOS2_STATUS_RSIE_MSK (0x00800000)
219 #define NIOS2_STATUS_SRS_MSK (0x80000000)
223 #define NIOS2_EXCEPTION_REG_CAUSE_MASK (0x0000007c)
225 #define NIOS2_EXCEPTION_REG_ECCFTL_MASK (0x80000000)
230 #define NIOS2_PTEADDR_REG_VPN_MASK 0x3ffffc
232 #define NIOS2_PTEADDR_REG_PTBASE_MASK 0xffc00000
235 #define NIOS2_TLBACC_REG_PFN_OFST 0
236 #define NIOS2_TLBACC_REG_PFN_MASK 0xfffff
238 #define NIOS2_TLBACC_REG_G_MASK 0x100000
240 #define NIOS2_TLBACC_REG_X_MASK 0x200000
242 #define NIOS2_TLBACC_REG_W_MASK 0x400000
244 #define NIOS2_TLBACC_REG_R_MASK 0x800000
246 #define NIOS2_TLBACC_REG_C_MASK 0x1000000
248 #define NIOS2_TLBACC_REG_IG_MASK 0xfe000000
251 #define NIOS2_TLBMISC_REG_D_OFST 0
252 #define NIOS2_TLBMISC_REG_D_MASK 0x1
254 #define NIOS2_TLBMISC_REG_PERM_MASK 0x2
256 #define NIOS2_TLBMISC_REG_BAD_MASK 0x4
258 #define NIOS2_TLBMISC_REG_DBL_MASK 0x8
260 #define NIOS2_TLBMISC_REG_PID_MASK 0x3fff0
262 #define NIOS2_TLBMISC_REG_WE_MASK 0x40000
264 #define NIOS2_TLBMISC_REG_RD_MASK 0x80000
266 #define NIOS2_TLBMISC_REG_WAY_MASK 0xf00000
268 #define NIOS2_TLBMISC_REG_EE_MASK 0x1000000
271 #define NIOS2_ECCINJ_REG_RF_OFST 0
272 #define NIOS2_ECCINJ_REG_RF_MASK 0x3
274 #define NIOS2_ECCINJ_REG_ICTAG_MASK 0xc
276 #define NIOS2_ECCINJ_REG_ICDAT_MASK 0x30
278 #define NIOS2_ECCINJ_REG_DCTAG_MASK 0xc0
280 #define NIOS2_ECCINJ_REG_DCDAT_MASK 0x300
282 #define NIOS2_ECCINJ_REG_TLB_MASK 0xc00
284 #define NIOS2_ECCINJ_REG_DTCM0_MASK 0x3000
286 #define NIOS2_ECCINJ_REG_DTCM1_MASK 0xc000
288 #define NIOS2_ECCINJ_REG_DTCM2_MASK 0x30000
290 #define NIOS2_ECCINJ_REG_DTCM3_MASK 0xc0000
293 #define NIOS2_CONFIG_REG_PE_MASK (0x00000001)
294 #define NIOS2_CONFIG_REG_PE_OFST (0)
295 #define NIOS2_CONFIG_REG_ANI_MASK (0x00000002)
297 #define NIOS2_CONFIG_REG_ECCEN_MASK (0x00000004)
299 #define NIOS2_CONFIG_REG_ECCEXC_MASK (0x00000008)
303 #define NIOS2_MPUBASE_D_MASK (0x00000001)
304 #define NIOS2_MPUBASE_D_OFST (0)
305 #define NIOS2_MPUBASE_INDEX_MASK (0x0000003e)
307 #define NIOS2_MPUBASE_BASE_ADDR_MASK (0xffffffc0)
311 #define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0)
313 #define NIOS2_MPUACC_MASK_MASK (0xffffffc0)
315 #define NIOS2_MPUACC_C_MASK (0x00000020)
317 #define NIOS2_MPUACC_PERM_MASK (0x0000001c)
319 #define NIOS2_MPUACC_RD_MASK (0x00000002)
321 #define NIOS2_MPUACC_WR_MASK (0x00000001)
322 #define NIOS2_MPUACC_WR_OFST (0)