Lines Matching +full:0 +full:x00000020
12 #define MSTATUS_UIE 0x00000001
13 #define MSTATUS_SIE 0x00000002
14 #define MSTATUS_HIE 0x00000004
15 #define MSTATUS_MIE 0x00000008
16 #define MSTATUS_UPIE 0x00000010
17 #define MSTATUS_SPIE 0x00000020
18 #define MSTATUS_HPIE 0x00000040
19 #define MSTATUS_MPIE 0x00000080
20 #define MSTATUS_SPP 0x00000100
21 #define MSTATUS_HPP 0x00000600
22 #define MSTATUS_MPP 0x00001800
23 #define MSTATUS_FS 0x00006000
24 #define MSTATUS_XS 0x00018000
25 #define MSTATUS_MPRV 0x00020000
26 #define MSTATUS_SUM 0x00040000
27 #define MSTATUS_MXR 0x00080000
28 #define MSTATUS_TVM 0x00100000
29 #define MSTATUS_TW 0x00200000
30 #define MSTATUS_TSR 0x00400000
31 #define MSTATUS32_SD 0x80000000
32 #define MSTATUS_UXL 0x0000000300000000
33 #define MSTATUS_SXL 0x0000000C00000000
34 #define MSTATUS64_SD 0x8000000000000000
36 #define SSTATUS_UIE 0x00000001
37 #define SSTATUS_SIE 0x00000002
38 #define SSTATUS_UPIE 0x00000010
39 #define SSTATUS_SPIE 0x00000020
40 #define SSTATUS_SPP 0x00000100
41 #define SSTATUS_FS 0x00006000
42 #define SSTATUS_XS 0x00018000
43 #define SSTATUS_SUM 0x00040000
44 #define SSTATUS_MXR 0x00080000
45 #define SSTATUS32_SD 0x80000000
46 #define SSTATUS_UXL 0x0000000300000000
47 #define SSTATUS64_SD 0x8000000000000000
62 #define DCSR_PRV (3<<0)
64 #define DCSR_CAUSE_NONE 0
71 #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
73 #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
77 #define MCONTROL_ACTION (0x3f<<12)
79 #define MCONTROL_MATCH (0xf<<7)
86 #define MCONTROL_LOAD (1<<0)
88 #define MCONTROL_TYPE_NONE 0
91 #define MCONTROL_ACTION_DEBUG_EXCEPTION 0
97 #define MCONTROL_MATCH_EQUAL 0
117 #define PRV_U 0
122 #define SATP32_MODE 0x80000000
123 #define SATP32_ASID 0x7FC00000
124 #define SATP32_PPN 0x003FFFFF
125 #define SATP64_MODE 0xF000000000000000
126 #define SATP64_ASID 0x0FFFF00000000000
127 #define SATP64_PPN 0x00000FFFFFFFFFFF
129 #define SATP_MODE_OFF 0
136 #define PMP_R 0x01
137 #define PMP_W 0x02
138 #define PMP_X 0x04
139 #define PMP_A 0x18
140 #define PMP_L 0x80
143 #define PMP_TOR 0x08
144 #define PMP_NA4 0x10
145 #define PMP_NAPOT 0x18
159 #define DEFAULT_RSTVEC 0x00001000
160 #define CLINT_BASE 0x02000000
161 #define CLINT_SIZE 0x000c0000
162 #define EXT_IO_BASE 0x40000000
163 #define DRAM_BASE 0x80000000
166 #define PTE_V 0x001 /* Valid */
167 #define PTE_R 0x002 /* Read */
168 #define PTE_W 0x004 /* Write */
169 #define PTE_X 0x008 /* Execute */
170 #define PTE_U 0x010 /* User */
171 #define PTE_G 0x020 /* Global */
172 #define PTE_A 0x040 /* Accessed */
173 #define PTE_D 0x080 /* Dirty */
174 #define PTE_SOFT 0x300 /* Reserved for Software */
188 __asm__ volatile ("csrr %0, " STRINGIFY(csr) \
196 __asm__ volatile ("csrw " STRINGIFY(csr) ", %0" \
205 __asm__ volatile ("csrrs %0, " STRINGIFY(csr) ", %1" \
214 __asm__ volatile ("csrs " STRINGIFY(csr) ", %0" \
222 __asm__ volatile ("csrrc %0, " STRINGIFY(csr) ", %1" \
231 __asm__ volatile ("csrc " STRINGIFY(csr) ", %0" \