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/Zephyr-latest/tests/kernel/fpu_sharing/generic/src/
Dfloat_regs_riscv_gcc.h9 * SPDX-License-Identifier: Apache-2.0
51 "mv t0, %0\n" in _load_all_float_registers()
53 RV_FPREG_LOAD "f0, 0(t0)\n" in _load_all_float_registers()
54 "add t0, t0, t1\n" in _load_all_float_registers()
55 RV_FPREG_LOAD "f1, 0(t0)\n" in _load_all_float_registers()
56 "add t0, t0, t1\n" in _load_all_float_registers()
57 RV_FPREG_LOAD "f2, 0(t0)\n" in _load_all_float_registers()
58 "add t0, t0, t1\n" in _load_all_float_registers()
59 RV_FPREG_LOAD "f3, 0(t0)\n" in _load_all_float_registers()
60 "add t0, t0, t1\n" in _load_all_float_registers()
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/Zephyr-latest/arch/riscv/core/
Dreset.S2 * Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
5 * SPDX-License-Identifier: Apache-2.0
37 * Remainder of asm-land initialization code before we can jump into
42 li t0, CONFIG_RV_BOOT_HART
43 beq a0, t0, boot_first_core
50 * Enable floating-point.
52 li t0, MSTATUS_FS_INIT
53 csrs mstatus, t0
56 * Floating-point rounding mode set to IEEE-754 default, and clear
63 /* Pre-populate all bytes in z_interrupt_stacks with 0xAA */
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Disr.S2 * Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
6 * SPDX-License-Identifier: Apache-2.0
27 RV_E( op t0, __struct_arch_esf_t0_OFFSET(sp) );\
45 /* Convenience macro for storing callee saved register [s0 - s11] states. */
110 * Generic architecture-level IRQ handling, along with callouts to
111 * SoC-specific routines.
117 * Since RISC-V does not completely prescribe IRQ handling behavior,
122 * - __soc_is_irq (optional): decide if we're handling an interrupt or an
124 * - __soc_handle_irq: handle SoC-specific details for a pending IRQ
125 * (e.g. clear a pending bit in a SoC-specific register)
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Dpmp.S4 * SPDX-License-Identifier: Apache-2.0
31 * known (luckily they're all power-of-2's simplifying the code further).
39 la t0, pmpaddr_store
40 slli t1, a0, 4 /* 16-byte instruction blocks */
41 add t0, t0, t1
42 jr t0
50 lr t0, (RV_REGSIZE * _index)(a3)
52 csrw (CSR_PMPADDR_BASE + _index), t0
63 * a1 = (a1 + RV_REGSIZE - 1) / RV_REGSIZE
65 la t0, pmpcfg_store
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Dfpu.S5 * SPDX-License-Identifier: Apache-2.0
57 frcsr t0
59 sw t0, __z_riscv_fp_context_t_fcsr_OFFSET(a0)
66 lw t0, __z_riscv_fp_context_t_fcsr_OFFSET(a0)
67 fscsr t0
/Zephyr-latest/soc/andestech/ae350/
Dstart.S4 * SPDX-License-Identifier: Apache-2.0
21 la t0, _ITB_BASE_
22 csrw NDS_UITB, t0
27 li t0, (1 << 9) | (1 << 0)
28 csrs NDS_MCACHE_CTL, t0
33 * Enable D cache with HW prefetcher, D-cache write-around
36 li t0, (0x3 << 13)
37 csrc NDS_MCACHE_CTL, t0
38 li t0, (1 << 19) | (1 << 13) | (1 << 10) | (1 << 1)
39 csrs NDS_MCACHE_CTL, t0
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Dsoc_irq.S4 * SPDX-License-Identifier: Apache-2.0
21 csrr t0, NDS_MXSTATUS
28 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
38 lw t0, __soc_esf_t_mxstatus_OFFSET(a0)
45 csrw NDS_MXSTATUS, t0
/Zephyr-latest/soc/telink/tlsr/tlsr951x/
Dstart.S4 * SPDX-License-Identifier: Apache-2.0
34 /* Enable I/D-Cache */
35 csrr t0, NDS_MCACHE_CTL
36 ori t0, t0, 1 #/I-Cache
37 ori t0, t0, 2 #/D-Cache
38 csrw NDS_MCACHE_CTL, t0
41 /* Enable misaligned access and non-blocking load */
42 li t0, (1 << 8) | (1 << 6)
43 csrs NDS_MMISC_CTL, t0
46 lui t0, 0
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Dsoc_irq.S4 * SPDX-License-Identifier: Apache-2.0
25 csrr t0, NDS_MXSTATUS
32 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
42 lw t0, __soc_esf_t_mxstatus_OFFSET(a0)
49 csrw NDS_MXSTATUS, t0
/Zephyr-latest/soc/nordic/common/vpr/
Dsoc_isr_stacking.h3 * SPDX-License-Identifier: Apache-2.0
28 unsigned long t0; \
52 unsigned long t0; \
76 #define ESF_SW_EXC_SIZEOF (__struct_arch_esf_SIZEOF - ESF_HW_SIZEOF)
94 lr t0, __struct_arch_esf_mepc_OFFSET(sp); \
95 andi t0, t0, MEPC_SP_ALIGN_BIT_MASK; \
96 sr t0, __soc_esf_t_sp_align_OFFSET(t1)
100 lr t0, __soc_esf_t_sp_align_OFFSET(t1); \
102 or t2, t1, t0; \
106 csrw mscratch, t0; \
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Dsoc_context.S3 * SPDX-License-Identifier: Apache-2.0
13 csrr t0, 0x347
14 sw t0, __soc_esf_t_minttresh_OFFSET(a0)
19 lw t0, __soc_esf_t_minttresh_OFFSET(a0)
20 csrw 0x347, t0
/Zephyr-latest/soc/common/riscv-privileged/
Dvector.S2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
5 * SPDX-License-Identifier: Apache-2.0
41 la t0, _isr_wrapper
43 add t0, zero, zero
45 addi t0, t0, 0x03 /* Enable CLIC vectored mode by setting LSB */
46 csrw mtvec, t0
60 la t0, _irq_vector_table
61 csrw 0x307, t0 /* mtvt */
68 * Set mtvec (Machine Trap-Vector Base-Address Register)
74 * NOTE: _irq_vector_table is 256-byte aligned. Incorrect alignment
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/Zephyr-latest/include/zephyr/arch/riscv/
Dsyscall.h4 * SPDX-License-Identifier: Apache-2.0
12 * included by the syscall interface architecture-abstraction header
36 * Syscall invocation macros. riscv-specific machine constraints used to ensure
50 register unsigned long t0 __asm__ ("t0") = call_id; in arch_syscall_invoke6()
55 "r" (t0) in arch_syscall_invoke6()
70 register unsigned long t0 __asm__ ("t0") = call_id; in arch_syscall_invoke5()
74 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (t0) in arch_syscall_invoke5()
87 register unsigned long t0 __asm__ ("t0") = call_id; in arch_syscall_invoke4()
91 : "r" (a1), "r" (a2), "r" (a3), "r" (t0) in arch_syscall_invoke4()
103 register unsigned long t0 __asm__ ("t0") = call_id; in arch_syscall_invoke3()
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/Zephyr-latest/soc/openisa/rv32m1/
Dsoc_irq.S4 * SPDX-License-Identifier: Apache-2.0
22 * EVENT_UNIT->INTPTPENDCLEAR = (1U << irq_num);
33 la t0, __EVENT_INTPTPENDCLEAR
36 sw t1, 0x00(t0)
46 * Zephyr's generic RISC-V mechanism for soc-specific context.
52 csrr t0, RI5CY_LPSTART0
55 sw t0, __soc_esf_t_lpstart0_OFFSET(a0)
58 csrr t0, RI5CY_LPSTART1
61 sw t0, __soc_esf_t_lpstart1_OFFSET(a0)
70 lw t0, __soc_esf_t_lpstart0_OFFSET(a0)
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/Zephyr-latest/soc/ite/ec/common/
Dvector.S5 * SPDX-License-Identifier: Apache-2.0
31 la t0, IT8XXX2_GCTRL_PMER3
32 lb t1, 0(t0)
34 sb t1, 0(t0)
36 la t0, IT8XXX2_JTAG_PINS_BASE
39 sb t1, 0(t0)
41 sb t1, 1(t0)
43 sb t1, 4(t0)
45 sb t1, 5(t0)
47 sb t1, 6(t0)
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/Zephyr-latest/samples/kernel/metairq_dispatch/
DREADME.rst17 Each message has a random (and non-trivial) amount of processing that
21 Messages are accompanied by a timestamp that allows per-message
43 priority will experience some load-dependent delays, as the CPU
72 .. zephyr-app-commands::
73 :zephyr-app: samples/kernel/metairq_dispatch
88 (intended) for non-cooperative threads like T2 and T3 which is attributed to delays
92 .. code-block:: console
94 I: Starting Thread0 at priority -2
95 I: Starting Thread1 at priority -1
96 II: M0 T0 mirq 4478 disp 7478 proc 24336 real 24613
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/Zephyr-latest/arch/mips/core/
Dreset.S4 * SPDX-License-Identifier: Apache-2.0
17 * Remainder of asm-land initialization code before we can jump into
33 /* Pre-populate all bytes in z_interrupt_stacks with 0xAA */
34 la t0, z_interrupt_stacks
36 add t1, t1, t0
41 sw t2, 0(t0)
42 addi t0, t0, 4
43 blt t0, t1, aa_loop
Disr.S6 * SPDX-License-Identifier: Apache-2.0
43 op t0, ESF_O(t0)(sp) ;\
61 addi sp, sp, -__struct_arch_esf_SIZEOF ;\
85 * Save caller-saved registers on current thread stack.
90 mfhi t0
92 OP_STOREREG t0, ESF_O(hi)(sp)
94 mfc0 t0, CP0_EPC
95 OP_STOREREG t0, ESF_O(epc)(sp)
98 mfc0 t0, CP0_STATUS
99 OP_STOREREG t0, ESF_O(status)(sp)
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/Zephyr-latest/dts/bindings/watchdog/
Dnuvoton,npcx-watchdog.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Nuvoton, NPCX-TWD node
6 compatible: "nuvoton,npcx-watchdog"
13 t0-out:
17 Mapping table between Wake-Up Input (WUI) and t0-out timer expired signal.
18 For example, the WUI mapping on NPCX7 t0-out timer would be
19 t0-out = <&wui_t0out>;
/Zephyr-latest/drivers/interrupt_controller/
Dintc_nuclei_eclic.S4 * SPDX-License-Identifier: Apache-2.0
8 * @brief Assembler-hooks specific to Nuclei's Extended Core Interrupt Controller
18 * In non-vectored mode, interrupts are cleared when writing the mnxti register (done in
34 * This function services and clears all pending interrupts for an ECLIC in non-vectored mode.
37 addi sp, sp, -16
52 * the mtvt, sw irq table is 2-pointer wide -> shift by one. */
53 csrr t0, 0x307 /* mtvt */
54 sub a0, a0, t0
55 la t0, _sw_isr_table
57 add t0, t0, a0
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/Zephyr-latest/dts/bindings/led_strip/
Dworldsemi,ws2812-rpi_pico-pio.yaml2 # SPDX-License-Identifier: Apache-2.0
7 compatible: "worldsemi,ws2812-rpi_pico-pio"
9 include: pinctrl-device.yaml
12 bit-waveform:
15 This property defines the waveform for sending 1-bit data.
17 The T0 is equal to T0H in the datasheet.
19 The T1 is equal to (T1H-T0H) or (T0L-T1L) in the datasheet.
21 Code-0
22 +------+ +---
24 | T0 | T1+T2 |
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/Zephyr-latest/soc/neorv32/
Dsoc_irq.S4 * SPDX-License-Identifier: Apache-2.0
12 * SOC-specific function to handle pending IRQ number generating the interrupt.
17 * The MIP CSR on the NEORV32 is read-only and can thus not be used for
19 * re-enable it (if it was enabled when clearing).
22 sll t0, t1, a0
23 csrrc t2, mie, t0
24 and t1, t2, t0
/Zephyr-latest/tests/kernel/tickless/tickless_concept/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
21 #define SLEEP_TICKFUL k_ticks_to_ms_floor64(IDLE_THRESH - 1)
71 volatile uint32_t t0, t1; in ZTEST() local
74 t0 = k_uptime_get_32(); in ZTEST()
77 TC_PRINT("time %d, %d\n", t0, t1); in ZTEST()
79 zassert_true((t1 - t0) >= SLEEP_TICKLESS); in ZTEST()
82 t0 = k_uptime_get_32(); in ZTEST()
85 TC_PRINT("time %d, %d\n", t0, t1); in ZTEST()
87 zassert_true((t1 - t0) >= SLEEP_TICKFUL); in ZTEST()
/Zephyr-latest/drivers/watchdog/
Dwdt_npcx.c4 * SPDX-License-Identifier: Apache-2.0
14 * clocks and interrupts (T0 Timer) used for its callback functions in the
18 * +---------------------+ +-----------------+
19 * LFCLK --->| T0 Prescale Counter |-+->| 16-Bit T0 Timer |--------> T0 Timer
21 * +---------------------+ | +-----------------+
22 * +---------------------------------+
24 * | +-------------------+ +-----------------+
25 * +--->| Watchdog Prescale |--->| 8-Bit Watchdog |-----> Watchdog Event/Reset
27 * +-------------------+ +-----------------+
50 * (TWCP) to 0x5. Since the watchdog counter is 8-bits, maximum time supported
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/Zephyr-latest/tests/subsys/fs/littlefs/src/
Dtest_lfs_perf.c4 * SPDX-License-Identifier: Apache-2.0
27 const struct lfs_config *lcp = &((const struct fs_littlefs *)mp->fs_data)->cfg; in write_read()
33 uint32_t t0; in write_read() local
41 mp->mnt_point, tag); in write_read()
48 TC_PRINT("Mount %s failed: %d\n", mp->mnt_point, rc); in write_read()
52 rc = fs_statvfs(mp->mnt_point, &vfs); in write_read()
54 TC_PRINT("statvfs %s failed: %d\n", mp->mnt_point, rc); in write_read()
59 mp->mnt_point, in write_read()
62 lcp->read_size, lcp->prog_size, lcp->cache_size, lcp->lookahead_size); in write_read()
70 TC_PRINT("Failed to allocate %zu-byte buffer\n", buf_size); in write_read()
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