Lines Matching +full:- +full:t0
2 * Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
6 * SPDX-License-Identifier: Apache-2.0
27 RV_E( op t0, __struct_arch_esf_t0_OFFSET(sp) );\
45 /* Convenience macro for storing callee saved register [s0 - s11] states. */
110 * Generic architecture-level IRQ handling, along with callouts to
111 * SoC-specific routines.
117 * Since RISC-V does not completely prescribe IRQ handling behavior,
122 * - __soc_is_irq (optional): decide if we're handling an interrupt or an
124 * - __soc_handle_irq: handle SoC-specific details for a pending IRQ
125 * (e.g. clear a pending bit in a SoC-specific register)
127 * If CONFIG_RISCV_SOC_CONTEXT_SAVE=y, calls to SoC-level context save/restore
143 /* preserve t0 and t1 temporarily */
144 sr t0, _curr_cpu_arch_user_exc_tmp0(s0)
148 csrr t0, mstatus
150 and t0, t0, t1
151 bnez t0, 1f
154 mv t0, sp
160 sr t0, (-__struct_arch_esf_SIZEOF + __struct_arch_esf_sp_OFFSET)(sp)
163 lr t0, ___cpu_t_current_OFFSET(s0)
164 lr tp, _thread_offset_to_tls(t0)
176 /* Clear our per-thread usermode flag */
177 lui t0, %tprel_hi(is_user_mode)
178 add t0, t0, tp, %tprel_add(is_user_mode)
179 sb zero, %tprel_lo(is_user_mode)(t0)
181 /* retrieve original t0/t1 values */
182 lr t0, _curr_cpu_arch_user_exc_tmp0(s0)
192 /* Save caller-saved registers on current thread stack. */
193 addi sp, sp, -__struct_arch_esf_SIZEOF
202 csrr t0, mepc
203 sr t0, __struct_arch_esf_mepc_OFFSET(sp)
228 lw t2, 0(t0) /* t0 = mepc */
231 andi t0, t2, 0x7f /* keep only the opcode bits */
234 * 0000111 = LOAD-FP
235 * 0100111 = STORE-FP
240 * 1010011 = OP-FP
242 xori t1, t0, 0b1010011 /* OP-FP */
244 ori t1, t0, 0b0100000
245 xori t1, t1, 0b0100111 /* LOAD-FP / STORE-FP */
247 ori t1, t0, 0b0001100
255 * CSR format: csr#[31-20] src[19-15] op[14-12] dst[11-7] SYSTEM[6-0]
259 xori t1, t0, 0b1110011 /* SYSTEM opcode */
261 srli t0, t2, 12
262 andi t0, t0, 0x3
263 beqz t0, 2f /* not a CSR insn */
264 srli t0, t2, 20 /* isolate the csr register number */
265 beqz t0, 2f /* 0=ustatus */
266 andi t0, t0, ~0x3 /* 1=fflags, 2=frm, 3=fcsr */
268 bnez t0, no_fp
270 beqz t0, is_fp
286 srli t0, t2, 8
288 andi t1, t0, 0b01100000
292 andi t1, t0, 0b00100000
302 no_fp: /* increment arch_current_thread()->arch.exception_depth */
303 lr t0, ___cpu_t_current_OFFSET(s0)
304 lb t1, _thread_offset_to_exception_depth(t0)
306 sb t1, _thread_offset_to_exception_depth(t0)
320 * (SOC dependent). Following the RISC-V architecture spec, the MSB
323 * SOCs (like pulpino or riscv-qemu), the MSB is never set to indicate
332 csrr t0, mcause
333 srli t0, t0, RISCV_MCAUSE_IRQ_POS
334 bnez t0, is_interrupt
339 * perform a context-switch or an IRQ offload. Otherwise call _Fault
342 csrr t0, mcause
344 and t0, t0, t2
351 beq t0, t1, is_kernel_syscall
359 beq t0, t1, is_user_syscall
366 csrr t0, mstatus
368 and t0, t0, t1
369 bnez t0, 1f
398 lr t0, __struct_arch_esf_mepc_OFFSET(sp)
399 addi t0, t0, 4
400 sr t0, __struct_arch_esf_mepc_OFFSET(sp)
403 /* Re-activate PMP for m-mode */
410 /* Determine what to do. Operation code is in t0. */
411 lr t0, __struct_arch_esf_t0_OFFSET(sp)
414 beqz t0, do_fault
418 beq t0, t1, do_irq_offload
423 bne t0, t1, skip_schedule
429 * When an ECALL is used for a context-switch, the current thread has
434 add t1, t1, -1
462 /* Allocate space for caller-saved registers on current thread stack */
463 addi sp, sp, -__callee_saved_t_SIZEOF
465 /* Save callee-saved registers to be passed as 3rd arg */
489 /* Increment _current_cpu->nested */
496 mv t0, sp
500 addi sp, sp, -16
501 sr t0, 0(sp)
522 /* It is safe to re-enable IRQs now */
540 lr t0, __struct_arch_esf_t0_OFFSET(sp)
543 addi sp, sp, -4
552 bltu t0, t1, valid_syscall_id
555 mv a0, t0
556 li t0, K_SYSCALL_BAD
562 slli t1, t0, RV_REGSHIFT # Determine offset from indice value
589 lr t0, __struct_arch_esf_mstatus_OFFSET(sp)
591 and t0, t0, t1
592 bnez t0, 1f
597 1: /* Re-activate PMP for m-mode */
605 /* Increment _current_cpu->nested */
612 mv t0, sp
617 * In RISC-V, stack pointer needs to be 16-byte aligned
619 addi sp, sp, -16
620 sr t0, 0(sp)
634 li t0, CONFIG_RISCV_MCAUSE_EXCEPTION_MASK
635 and a0, a0, t0
645 * (table is 2-word wide, we should shift index accordingly)
647 la t0, _sw_isr_table
649 add t0, t0, a0
652 lr a0, 0(t0)
655 lr t1, RV_REGSIZE(t0)
667 /* Decrement _current_cpu->nested */
669 addi t2, t2, -1
692 addi sp, sp, -16
729 /* decrement arch_current_thread()->arch.exception_depth */
730 lr t0, ___cpu_t_current_OFFSET(s0)
731 lb t1, _thread_offset_to_exception_depth(t0)
732 add t1, t1, -1
733 sb t1, _thread_offset_to_exception_depth(t0)
738 lr t0, __struct_arch_esf_mepc_OFFSET(sp)
740 csrw mepc, t0
750 and t0, t2, t1
751 bnez t0, 1f
759 /* Set our per-thread usermode flag */
761 lui t0, %tprel_hi(is_user_mode)
762 add t0, t0, tp, %tprel_add(is_user_mode)
763 sb t1, %tprel_lo(is_user_mode)(t0)
766 add t0, sp, __struct_arch_esf_SIZEOF
767 sr t0, _curr_cpu_arch_user_exc_sp(s0)
773 * be re-loaded further down.
775 addi t0, sp, __struct_arch_esf_SIZEOF
776 sr t0, __struct_arch_esf_sp_OFFSET(sp)
786 /* Restore caller-saved registers from thread stack */