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Searched defs:v (Results 1 – 25 of 94) sorted by relevance

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/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_common.h18 #define z_pllm(v) LL_RCC_PLLM_DIV_ ## v argument
19 #define pllm(v) z_pllm(v) argument
21 #define z_pllp(v) LL_RCC_PLLP_DIV_ ## v argument
22 #define pllp(v) z_pllp(v) argument
24 #define z_pllq(v) LL_RCC_PLLQ_DIV_ ## v argument
25 #define pllq(v) z_pllq(v) argument
27 #define z_pllr(v) LL_RCC_PLLR_DIV_ ## v argument
28 #define pllr(v) z_pllr(v) argument
32 #define z_plli2s_m(v) LL_RCC_PLLI2SM_DIV_ ## v argument
35 #define z_plli2s_m(v) LL_RCC_PLLM_DIV_ ## v argument
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Dclock_stm32_ll_common.c23 #define z_hsi_divider(v) LL_RCC_HSI_DIV_ ## v argument
24 #define hsi_divider(v) z_hsi_divider(v) argument
27 #define fn_ahb_prescaler(v) LL_RCC_HCLK_DIV_ ## v argument
28 #define ahb_prescaler(v) fn_ahb_prescaler(v) argument
30 #define fn_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v argument
31 #define ahb_prescaler(v) fn_ahb_prescaler(v) argument
34 #define fn_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v argument
35 #define apb1_prescaler(v) fn_apb1_prescaler(v) argument
38 #define fn_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v argument
39 #define apb2_prescaler(v) fn_apb2_prescaler(v) argument
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Dclock_stm32l0_l1.c22 #define z_pll_mul(v) LL_RCC_PLL_MUL_ ## v argument
23 #define pll_mul(v) z_pll_mul(v) argument
25 #define z_pll_div(v) LL_RCC_PLL_DIV_ ## v argument
26 #define pll_div(v) z_pll_div(v) argument
Dclock_stm32_ll_wba.c20 #define fn_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v argument
21 #define ahb_prescaler(v) fn_ahb_prescaler(v) argument
23 #define fn_ahb5_prescaler(v) LL_RCC_AHB5_DIV_ ## v argument
24 #define ahb5_prescaler(v) fn_ahb5_prescaler(v) argument
26 #define fn_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v argument
27 #define apb1_prescaler(v) fn_apb1_prescaler(v) argument
29 #define fn_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v argument
30 #define apb2_prescaler(v) fn_apb2_prescaler(v) argument
32 #define fn_apb7_prescaler(v) LL_RCC_APB7_DIV_ ## v argument
33 #define apb7_prescaler(v) fn_apb7_prescaler(v) argument
Dclock_stm32_ll_h7.c24 #define z_hsi_divider(v) LL_RCC_HSI_DIV_ ## v argument
26 #define z_hsi_divider(v) LL_RCC_HSI_DIV ## v argument
28 #define hsi_divider(v) z_hsi_divider(v) argument
30 #define z_sysclk_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v argument
31 #define sysclk_prescaler(v) z_sysclk_prescaler(v) argument
33 #define z_ahb_prescaler(v) LL_RCC_AHB_DIV_ ## v argument
34 #define ahb_prescaler(v) z_ahb_prescaler(v) argument
36 #define z_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v argument
37 #define apb1_prescaler(v) z_apb1_prescaler(v) argument
39 #define z_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v argument
[all …]
Dclock_stm32_ll_h5.c23 #define z_hsi_divider(v) LL_RCC_HSI_DIV_ ## v argument
24 #define hsi_divider(v) z_hsi_divider(v) argument
26 #define z_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v argument
27 #define ahb_prescaler(v) z_ahb_prescaler(v) argument
29 #define z_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v argument
30 #define apb1_prescaler(v) z_apb1_prescaler(v) argument
32 #define z_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v argument
33 #define apb2_prescaler(v) z_apb2_prescaler(v) argument
35 #define z_apb3_prescaler(v) LL_RCC_APB3_DIV_ ## v argument
36 #define apb3_prescaler(v) z_apb3_prescaler(v) argument
Dclock_stm32_ll_u5.c23 #define z_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v argument
24 #define ahb_prescaler(v) z_ahb_prescaler(v) argument
26 #define z_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v argument
27 #define apb1_prescaler(v) z_apb1_prescaler(v) argument
29 #define z_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v argument
30 #define apb2_prescaler(v) z_apb2_prescaler(v) argument
32 #define z_apb3_prescaler(v) LL_RCC_APB3_DIV_ ## v argument
33 #define apb3_prescaler(v) z_apb3_prescaler(v) argument
/Zephyr-latest/soc/nxp/s32/s32k3/
Dpmc.c15 #define PMC_LVSC_HVDAF(v) FIELD_PREP(PMC_LVSC_HVDAF_MASK, (v)) argument
17 #define PMC_LVSC_HVDBF(v) FIELD_PREP(PMC_LVSC_HVDBF_MASK, (v)) argument
19 #define PMC_LVSC_HVD25F(v) FIELD_PREP(PMC_LVSC_HVD25F_MASK, (v)) argument
21 #define PMC_LVSC_HVD11F(v) FIELD_PREP(PMC_LVSC_HVD11F_MASK, (v)) argument
23 #define PMC_LVSC_LVD5AF(v) FIELD_PREP(PMC_LVSC_LVD5AF_MASK, (v)) argument
25 #define PMC_LVSC_LVD15F(v) FIELD_PREP(PMC_LVSC_LVD15F_MASK, (v)) argument
27 #define PMC_LVSC_HVDAS(v) FIELD_PREP(PMC_LVSC_HVDAS_MASK, (v)) argument
29 #define PMC_LVSC_HVDBS(v) FIELD_PREP(PMC_LVSC_HVDBS_MASK, (v)) argument
31 #define PMC_LVSC_HVD25S(v) FIELD_PREP(PMC_LVSC_HVD25S_MASK, (v)) argument
33 #define PMC_LVSC_HVD11S(v) FIELD_PREP(PMC_LVSC_HVD11S_MASK, (v)) argument
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Dpinctrl_soc.h17 #define SIUL2_MSCR_SSS(v) FIELD_PREP(SIUL2_MSCR_SSS_MASK, (v)) argument
19 #define SIUL2_MSCR_SMC(v) FIELD_PREP(SIUL2_MSCR_SMC_MASK, (v)) argument
21 #define SIUL2_MSCR_IFE(v) FIELD_PREP(SIUL2_MSCR_IFE_MASK, (v)) argument
23 #define SIUL2_MSCR_DSE(v) FIELD_PREP(SIUL2_MSCR_DSE_MASK, (v)) argument
25 #define SIUL2_MSCR_PUS(v) FIELD_PREP(SIUL2_MSCR_PUS_MASK, (v)) argument
27 #define SIUL2_MSCR_PUE(v) FIELD_PREP(SIUL2_MSCR_PUE_MASK, (v)) argument
29 #define SIUL2_MSCR_SRC(v) FIELD_PREP(SIUL2_MSCR_SRC_MASK, (v)) argument
31 #define SIUL2_MSCR_PKE(v) FIELD_PREP(SIUL2_MSCR_PKE_MASK, (v)) argument
33 #define SIUL2_MSCR_INV(v) FIELD_PREP(SIUL2_MSCR_INV_MASK, (v)) argument
35 #define SIUL2_MSCR_IBE(v) FIELD_PREP(SIUL2_MSCR_IBE_MASK, (v)) argument
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/Zephyr-latest/soc/nxp/s32/s32ze/
Dpinctrl_soc.h17 #define SIUL2_MSCR_SSS(v) FIELD_PREP(SIUL2_MSCR_SSS_MASK, (v)) argument
19 #define SIUL2_MSCR_SMC(v) FIELD_PREP(SIUL2_MSCR_SMC_MASK, (v)) argument
21 #define SIUL2_MSCR_TRC(v) FIELD_PREP(SIUL2_MSCR_TRC_MASK, (v)) argument
23 #define SIUL2_MSCR_RCVR(v) FIELD_PREP(SIUL2_MSCR_RCVR_MASK, (v)) argument
25 #define SIUL2_MSCR_CREF(v) FIELD_PREP(SIUL2_MSCR_CREF_MASK, (v)) argument
27 #define SIUL2_MSCR_PUS(v) FIELD_PREP(SIUL2_MSCR_PUS_MASK, (v)) argument
29 #define SIUL2_MSCR_PUE(v) FIELD_PREP(SIUL2_MSCR_PUE_MASK, (v)) argument
31 #define SIUL2_MSCR_SRE(v) FIELD_PREP(SIUL2_MSCR_SRE_MASK, (v)) argument
33 #define SIUL2_MSCR_RXCB(v) FIELD_PREP(SIUL2_MSCR_RXCB_MASK, (v)) argument
35 #define SIUL2_MSCR_IBE(v) FIELD_PREP(SIUL2_MSCR_IBE_MASK, (v)) argument
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/Zephyr-latest/soc/nxp/s32/common/
Dmc_rgm.c15 #define MC_RGM_DES_F_POR(v) FIELD_PREP(MC_RGM_DES_F_POR_MASK, (v)) argument
19 #define MC_RGM_FES_F_EXR(v) FIELD_PREP(MC_RGM_FES_F_EXR_MASK, (v)) argument
27 #define MC_RGM_FREC_FREC(v) FIELD_PREP(MC_RGM_FREC_FREC_MASK, (v)) argument
31 #define MC_RGM_FRET_FRET(v) FIELD_PREP(MC_RGM_FRET_FRET_MASK, (v)) argument
35 #define MC_RGM_DRET_DRET(v) FIELD_PREP(MC_RGM_DRET_DRET_MASK, (v)) argument
39 #define MC_RGM_ERCTRL_ERASSERT(v) FIELD_PREP(MC_RGM_ERCTRL_ERASSERT_MASK, (v)) argument
43 #define MC_RGM_RDSS_DES_RES(v) FIELD_PREP(MC_RGM_RDSS_DES_RES_MASK, (v)) argument
45 #define MC_RGM_RDSS_FES_RES(v) FIELD_PREP(MC_RGM_RDSS_FES_RES_MASK, (v)) argument
49 #define MC_RGM_FRENTC_FRET_EN(v) FIELD_PREP(MC_RGM_FRENTC_FRET_EN_MASK, (v)) argument
51 #define MC_RGM_FRENTC_FRET_TIMEOUT(v) FIELD_PREP(MC_RGM_FRENTC_FRET_TIMEOUT_MASK, (v)) argument
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Dmc_me.c17 #define MC_ME_CTL_KEY_KEY(v) FIELD_PREP(MC_ME_CTL_KEY_KEY_MASK, (v)) argument
21 #define MC_ME_MODE_CONF_DEST_RST(v) FIELD_PREP(MC_ME_MODE_CONF_DEST_RST_MASK, (v)) argument
23 #define MC_ME_MODE_CONF_FUNC_RST(v) FIELD_PREP(MC_ME_MODE_CONF_FUNC_RST_MASK, (v)) argument
25 #define MC_ME_MODE_CONF_STANDBY(v) FIELD_PREP(MC_ME_MODE_CONF_STANDBY_MASK, (v)) argument
29 #define MC_ME_MODE_UPD_MODE_UPD(v) FIELD_PREP(MC_ME_MODE_UPD_MODE_UPD_MASK, (v)) argument
33 #define MC_ME_MODE_STAT_PREV_MODE(v) FIELD_PREP(MC_ME_MODE_STAT_PREV_MODE_MASK, (v)) argument
37 #define MC_ME_MAIN_COREID_CIDX(v) FIELD_PREP(MC_ME_MAIN_COREID_CIDX_MASK, (v)) argument
39 #define MC_ME_MAIN_COREID_PIDX(v) FIELD_PREP(MC_ME_MAIN_COREID_PIDX_MASK, (v)) argument
43 #define MC_ME_PRTN_PCONF_PCE(v) FIELD_PREP(MC_ME_PRTN_PCONF_PCE_MASK, (v)) argument
47 #define MC_ME_PRTN_PUPD_PCUD(v) FIELD_PREP(MC_ME_PRTN_PUPD_PCUD_MASK, (v)) argument
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/Zephyr-latest/drivers/watchdog/
Dwdt_nxp_s32.c22 #define SWT_CR_WEN(v) FIELD_PREP(SWT_CR_WEN_MASK, (v)) argument
24 #define SWT_CR_FRZ(v) FIELD_PREP(SWT_CR_FRZ_MASK, (v)) argument
26 #define SWT_CR_STP(v) FIELD_PREP(SWT_CR_STP_MASK, (v)) argument
28 #define SWT_CR_SLK(v) FIELD_PREP(SWT_CR_SLK_MASK, (v)) argument
30 #define SWT_CR_HLK(v) FIELD_PREP(SWT_CR_HLK_MASK, (v)) argument
32 #define SWT_CR_ITR(v) FIELD_PREP(SWT_CR_ITR_MASK, (v)) argument
34 #define SWT_CR_WND(v) FIELD_PREP(SWT_CR_WND_MASK, (v)) argument
36 #define SWT_CR_RIA(v) FIELD_PREP(SWT_CR_RIA_MASK, (v)) argument
38 #define SWT_CR_SMD(v) FIELD_PREP(SWT_CR_SMD_MASK, (v)) argument
40 #define SWT_CR_MAP(v) FIELD_PREP(SWT_CR_MAP_MASK, (v)) argument
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/Zephyr-latest/subsys/logging/
Dlog_output_syst.c78 struct stp_writer_data *p, mipi_syst_u8 v) in stp_write_d4()
84 struct stp_writer_data *p, mipi_syst_u8 v) in stp_write_payload8()
91 struct stp_writer_data *p, mipi_syst_u16 v) in stp_write_payload16()
98 struct stp_writer_data *p, mipi_syst_u32 v) in stp_write_payload32()
105 struct stp_writer_data *p, mipi_syst_u64 v) in stp_write_payload64()
120 struct stp_writer_data *p, mipi_syst_u32 v) in stp_write_d32mts()
130 struct stp_writer_data *p, mipi_syst_u64 v) in stp_write_d64mts()
140 struct stp_writer_data *p, mipi_syst_u32 v) in stp_write_d32ts()
152 struct stp_writer_data *p, mipi_syst_u8 v) in stp_write_d8()
159 struct stp_writer_data *p, mipi_syst_u16 v) in stp_write_d16()
[all …]
/Zephyr-latest/soc/espressif/esp32/
Dsoc.h25 static inline void esp32_set_mask32(uint32_t v, uint32_t mem_addr) in esp32_set_mask32()
30 static inline void esp32_clear_mask32(uint32_t v, uint32_t mem_addr) in esp32_clear_mask32()
/Zephyr-latest/soc/espressif/esp32s3/
Dsoc.h30 static inline void esp32_set_mask32(uint32_t v, uint32_t mem_addr) in esp32_set_mask32()
35 static inline void esp32_clear_mask32(uint32_t v, uint32_t mem_addr) in esp32_clear_mask32()
/Zephyr-latest/drivers/sensor/tdk/icm42605/
Dicm42605_setup.c151 uint8_t v; in icm42605_sensor_init() local
243 uint8_t v = 0; in icm42605_turn_on_fifo() local
326 uint8_t v = 0; in icm42605_turn_off_fifo() local
393 uint8_t v = 0; in icm42605_turn_on_sensor() local
429 uint8_t v = 0; in icm42605_turn_off_sensor() local
/Zephyr-latest/drivers/edac/
Dibecc.h144 #define INTER_CHAN_DDR_TYPE(v) BITFIELD(v, 2, 0) argument
146 #define INTER_CHAN_ECHM(v) BITFIELD(v, 3, 3) argument
148 #define INTER_CHAN_CH_L_MAP(v) BITFIELD(v, 4, 4) argument
155 #define DIMM_L_MAP(v) BITFIELD(v, 0, 0) argument
160 #define DIMM_L_SIZE(v) (BITFIELD(v, 6, 0) << 29) argument
162 #define DIMM_L_WIDTH(v) BITFIELD(v, 8, 7) argument
164 #define DIMM_S_SIZE(v) (BITFIELD(v, 22, 16) << 29) argument
166 #define DIMM_S_WIDTH(v) BITFIELD(v, 25, 24) argument
/Zephyr-latest/drivers/charger/
Dcharger_bq24190.c73 uint8_t v; in bq24190_charger_get_charge_type() local
108 uint8_t v; in bq24190_charger_get_health() local
252 uint8_t v; in bq24190_charger_get_constant_charge_current() local
277 uint8_t v; in bq24190_charger_get_precharge_current() local
306 uint8_t v; in bq24190_charger_get_charge_term_current() local
324 uint8_t v; in bq24190_get_constant_charge_voltage() local
342 uint8_t v; in bq24190_set_constant_charge_current() local
368 uint8_t v; in bq24190_set_constant_charge_voltage() local
/Zephyr-latest/include/zephyr/arch/xtensa/
Darch_inlines.h34 #define XTENSA_WSR(sr, v) \ argument
57 #define XTENSA_WUR(ur, v) \ argument
/Zephyr-latest/samples/subsys/usb_c/source/src/
Dpower_ctrl.c45 int vconn_ctrl_set(enum vconn_t v) in vconn_ctrl_set()
65 int source_ctrl_set(enum source_t v) in source_ctrl_set()
/Zephyr-latest/subsys/testsuite/coverage/
Dcoverage.c41 static inline void print_u8(uint8_t v) in print_u8()
49 static inline void print_u32(uint32_t v) in print_u32()
63 static inline void write_u64(void *buffer, size_t *off, uint64_t v) in write_u64()
77 static inline void write_u32(void *buffer, size_t *off, uint32_t v) in write_u32()
/Zephyr-latest/samples/subsys/zbus/dyn_channel/src/
Dmain.c77 const struct version_msg *v = zbus_chan_const_msg(&version_chan); in main() local
/Zephyr-latest/drivers/counter/
Dcounter_nxp_s32_sys_timer.c24 #define STM_CR_TEN(v) FIELD_PREP(STM_CR_TEN_MASK, (v)) argument
26 #define STM_CR_FRZ(v) FIELD_PREP(STM_CR_FRZ_MASK, (v)) argument
28 #define STM_CR_CPS(v) FIELD_PREP(STM_CR_CPS_MASK, (v)) argument
32 #define STM_CNT_CNT(v) FIELD_PREP(STM_CNT_CNT_MASK, (v)) argument
36 #define STM_CCR_CEN(v) FIELD_PREP(STM_CCR_CEN_MASK, (v)) argument
40 #define STM_CIR_CIF(v) FIELD_PREP(STM_CIR_CIF_MASK, (v)) argument
44 #define STM_CMP_CMP(v) FIELD_PREP(STM_CMP_CMP_MASK, (v)) argument
48 #define REG_WRITE(r, v) sys_write32((v), config->base + (r)) argument
/Zephyr-latest/include/zephyr/sensing/
Dsensing_datatypes.h82 q31_t v[3]; member
107 uint32_t v; member
127 q31_t v; member

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