Searched defs:CTRL (Results 1 – 15 of 15) sorted by relevance
475 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member528 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
491 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member544 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
561 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member613 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member858 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member964 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
451 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
694 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member821 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member1131 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1046 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member1185 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member1370 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member1606 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member1718 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
711 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member838 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member1148 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
477 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
776 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member903 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member1213 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
984 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member1135 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member1452 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member1567 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
995 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member1122 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member1435 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1140 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member1291 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member2184 __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ member2954 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member3069 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
1101 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member1252 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member2147 __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ member2917 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member3032 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
1101 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member1252 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member2171 __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ member2941 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member3056 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
