1 /*
2 * Copyright (c) 2009-2024 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * CMSIS Cortex-M23 Core Peripheral Access Layer Header File
21 */
22
23 #if defined ( __ICCARM__ )
24 #pragma system_include /* treat file as system include file for MISRA check */
25 #elif defined (__clang__)
26 #pragma clang system_header /* treat file as system include file */
27 #elif defined ( __GNUC__ )
28 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
29 #endif
30
31 #ifndef __CORE_CM23_H_GENERIC
32 #define __CORE_CM23_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup Cortex_M23
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS CM23 definitions */
66
67 #define __CORTEX_M (23U) /*!< Cortex-M Core */
68
69 /** __FPU_USED indicates whether an FPU is used or not.
70 This core does not support an FPU at all
71 */
72 #define __FPU_USED 0U
73
74 #if defined ( __CC_ARM )
75 #if defined (__TARGET_FPU_VFP)
76 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
77 #endif
78
79 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
80 #if defined (__ARM_FP)
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82 #endif
83
84 #elif defined (__ti__)
85 #if defined (__ARM_FP)
86 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
87 #endif
88
89 #elif defined ( __GNUC__ )
90 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
91 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
92 #endif
93
94 #elif defined ( __ICCARM__ )
95 #if defined (__ARMVFP__)
96 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
97 #endif
98
99 #elif defined ( __TI_ARM__ )
100 #if defined (__TI_VFP_SUPPORT__)
101 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
102 #endif
103
104 #elif defined ( __TASKING__ )
105 #if defined (__FPU_VFP__)
106 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
107 #endif
108
109 #elif defined ( __CSMC__ )
110 #if ( __CSMC__ & 0x400U)
111 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
112 #endif
113
114 #endif
115
116 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
117
118
119 #ifdef __cplusplus
120 }
121 #endif
122
123 #endif /* __CORE_CM23_H_GENERIC */
124
125 #ifndef __CMSIS_GENERIC
126
127 #ifndef __CORE_CM23_H_DEPENDANT
128 #define __CORE_CM23_H_DEPENDANT
129
130 #ifdef __cplusplus
131 extern "C" {
132 #endif
133
134 /* check device defines and use defaults */
135 #if defined __CHECK_DEVICE_DEFINES
136 #ifndef __CM23_REV
137 #define __CM23_REV 0x0000U
138 #warning "__CM23_REV not defined in device header file; using default!"
139 #endif
140
141 #ifndef __FPU_PRESENT
142 #define __FPU_PRESENT 0U
143 #warning "__FPU_PRESENT not defined in device header file; using default!"
144 #endif
145
146 #ifndef __MPU_PRESENT
147 #define __MPU_PRESENT 0U
148 #warning "__MPU_PRESENT not defined in device header file; using default!"
149 #endif
150
151 #ifndef __SAUREGION_PRESENT
152 #define __SAUREGION_PRESENT 0U
153 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
154 #endif
155
156 #ifndef __VTOR_PRESENT
157 #define __VTOR_PRESENT 0U
158 #warning "__VTOR_PRESENT not defined in device header file; using default!"
159 #endif
160
161 #ifndef __NVIC_PRIO_BITS
162 #define __NVIC_PRIO_BITS 2U
163 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
164 #endif
165
166 #ifndef __Vendor_SysTickConfig
167 #define __Vendor_SysTickConfig 0U
168 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
169 #endif
170
171 #ifndef __ETM_PRESENT
172 #define __ETM_PRESENT 0U
173 #warning "__ETM_PRESENT not defined in device header file; using default!"
174 #endif
175
176 #ifndef __MTB_PRESENT
177 #define __MTB_PRESENT 0U
178 #warning "__MTB_PRESENT not defined in device header file; using default!"
179 #endif
180
181 #endif
182
183 /* IO definitions (access restrictions to peripheral registers) */
184 /**
185 \defgroup CMSIS_glob_defs CMSIS Global Defines
186
187 <strong>IO Type Qualifiers</strong> are used
188 \li to specify the access to peripheral variables.
189 \li for automatic generation of peripheral register debug information.
190 */
191 #ifdef __cplusplus
192 #define __I volatile /*!< Defines 'read only' permissions */
193 #else
194 #define __I volatile const /*!< Defines 'read only' permissions */
195 #endif
196 #define __O volatile /*!< Defines 'write only' permissions */
197 #define __IO volatile /*!< Defines 'read / write' permissions */
198
199 /* following defines should be used for structure members */
200 #define __IM volatile const /*! Defines 'read only' structure member permissions */
201 #define __OM volatile /*! Defines 'write only' structure member permissions */
202 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
203
204 /*@} end of group Cortex_M23 */
205
206
207
208 /*******************************************************************************
209 * Register Abstraction
210 Core Register contain:
211 - Core Register
212 - Core NVIC Register
213 - Core SCB Register
214 - Core SysTick Register
215 - Core Debug Register
216 - Core MPU Register
217 - Core SAU Register
218 ******************************************************************************/
219 /**
220 \defgroup CMSIS_core_register Defines and Type Definitions
221 \brief Type definitions and defines for Cortex-M processor based devices.
222 */
223
224 /**
225 \ingroup CMSIS_core_register
226 \defgroup CMSIS_CORE Status and Control Registers
227 \brief Core Register type definitions.
228 @{
229 */
230
231 /**
232 \brief Union type to access the Application Program Status Register (APSR).
233 */
234 typedef union
235 {
236 struct
237 {
238 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
239 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
240 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
241 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
242 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
243 } b; /*!< Structure used for bit access */
244 uint32_t w; /*!< Type used for word access */
245 } APSR_Type;
246
247 /** \brief APSR Register Definitions */
248 #define APSR_N_Pos 31U /*!< APSR: N Position */
249 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
250
251 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
252 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
253
254 #define APSR_C_Pos 29U /*!< APSR: C Position */
255 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
256
257 #define APSR_V_Pos 28U /*!< APSR: V Position */
258 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
259
260
261 /**
262 \brief Union type to access the Interrupt Program Status Register (IPSR).
263 */
264 typedef union
265 {
266 struct
267 {
268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
270 } b; /*!< Structure used for bit access */
271 uint32_t w; /*!< Type used for word access */
272 } IPSR_Type;
273
274 /** \brief IPSR Register Definitions */
275 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
277
278
279 /**
280 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
281 */
282 typedef union
283 {
284 struct
285 {
286 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
287 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
288 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
289 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
294 } b; /*!< Structure used for bit access */
295 uint32_t w; /*!< Type used for word access */
296 } xPSR_Type;
297
298 /** \brief xPSR Register Definitions */
299 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
301
302 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
304
305 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
307
308 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
310
311 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
312 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
313
314 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
315 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
316
317
318 /**
319 \brief Union type to access the Control Registers (CONTROL).
320 */
321 typedef union
322 {
323 struct
324 {
325 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
326 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
327 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
328 } b; /*!< Structure used for bit access */
329 uint32_t w; /*!< Type used for word access */
330 } CONTROL_Type;
331
332 /** \brief CONTROL Register Definitions */
333 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
334 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
335
336 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
337 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
338
339 /*@} end of group CMSIS_CORE */
340
341
342 /**
343 \ingroup CMSIS_core_register
344 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
345 \brief Type definitions for the NVIC Registers
346 @{
347 */
348
349 /**
350 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
351 */
352 typedef struct
353 {
354 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
355 uint32_t RESERVED0[16U];
356 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
357 uint32_t RESERVED1[16U];
358 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
359 uint32_t RESERVED2[16U];
360 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
361 uint32_t RESERVED3[16U];
362 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
363 uint32_t RESERVED4[16U];
364 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
365 uint32_t RESERVED5[16U];
366 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
367 } NVIC_Type;
368
369 /*@} end of group CMSIS_NVIC */
370
371
372 /**
373 \ingroup CMSIS_core_register
374 \defgroup CMSIS_SCB System Control Block (SCB)
375 \brief Type definitions for the System Control Block Registers
376 @{
377 */
378
379 /**
380 \brief Structure type to access the System Control Block (SCB).
381 */
382 typedef struct
383 {
384 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
385 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
386 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
387 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
388 #else
389 uint32_t RESERVED0;
390 #endif
391 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
392 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
393 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
394 uint32_t RESERVED1;
395 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
396 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
397 } SCB_Type;
398
399 /** \brief SCB CPUID Register Definitions */
400 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
401 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
402
403 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
404 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
405
406 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
407 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
408
409 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
410 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
411
412 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
413 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
414
415 /** \brief SCB Interrupt Control State Register Definitions */
416 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
417 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
418
419 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
420 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
421
422 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
423 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
424
425 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
426 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
427
428 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
429 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
430
431 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
432 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
433
434 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
435 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
436
437 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
438 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
439
440 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
441 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
442
443 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
444 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
445
446 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
447 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
448
449 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
450 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
451
452 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
453 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
454
455 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
456 /** \brief SCB Vector Table Offset Register Definitions */
457 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
458 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
459 #endif
460
461 /** \brief SCB Application Interrupt and Reset Control Register Definitions */
462 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
463 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
464
465 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
466 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
467
468 #define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */
469 #define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */
470
471 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
472 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
473
474 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
475 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
476
477 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
478 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
479
480 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
481 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
482
483 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
484 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
485
486 /** \brief SCB System Control Register Definitions */
487 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
488 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
489
490 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
491 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
492
493 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
494 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
495
496 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
497 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
498
499 /** \brief SCB Configuration Control Register Definitions */
500 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
501 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
502
503 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
504 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
505
506 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
507 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
508
509 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
510 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
511
512 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
513 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
514
515 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
516 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
517
518 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
519 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
520
521 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
522 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
523
524 /** \brief SCB System Handler Control and State Register Definitions */
525 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
526 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
527
528 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
529 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
530
531 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
532 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
533
534 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
535 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
536
537 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
538 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
539
540 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
541 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
542
543 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
544 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
545
546 /*@} end of group CMSIS_SCB */
547
548
549 /**
550 \ingroup CMSIS_core_register
551 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
552 \brief Type definitions for the System Timer Registers.
553 @{
554 */
555
556 /**
557 \brief Structure type to access the System Timer (SysTick).
558 */
559 typedef struct
560 {
561 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
562 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
563 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
564 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
565 } SysTick_Type;
566
567 /** \brief SysTick Control / Status Register Definitions */
568 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
569 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
570
571 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
572 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
573
574 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
575 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
576
577 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
578 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
579
580 /** \brief SysTick Reload Register Definitions */
581 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
582 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
583
584 /** \brief SysTick Current Register Definitions */
585 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
586 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
587
588 /** \brief SysTick Calibration Register Definitions */
589 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
590 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
591
592 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
593 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
594
595 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
596 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
597
598 /*@} end of group CMSIS_SysTick */
599
600
601 /**
602 \ingroup CMSIS_core_register
603 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
604 \brief Type definitions for the Data Watchpoint and Trace (DWT)
605 @{
606 */
607
608 /**
609 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
610 */
611 typedef struct
612 {
613 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
614 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
615 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
616 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
617 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
618 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
619 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
620 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
621 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
622 uint32_t RESERVED1[1U];
623 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
624 uint32_t RESERVED2[1U];
625 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
626 uint32_t RESERVED3[1U];
627 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
628 uint32_t RESERVED14[992U];
629 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */
630 } DWT_Type;
631
632 /** \brief DWT Control Register Definitions */
633 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
634 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
635
636 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
637 #define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
638
639 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
640 #define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
641
642 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
643 #define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
644
645 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
646 #define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
647
648 /** \brief DWT Comparator Function Register Definitions */
649 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
650 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
651
652 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
653 #define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
654
655 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
656 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
657
658 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
659 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
660
661 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
662 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
663
664 /*@}*/ /* end of group CMSIS_DWT */
665
666
667 /**
668 \ingroup CMSIS_core_register
669 \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU)
670 \brief Type definitions for the Trace Port Interface Unit (TPIU)
671 @{
672 */
673
674 /**
675 \brief Structure type to access the Trace Port Interface Unit Register (TPIU).
676 */
677 typedef struct
678 {
679 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
680 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
681 uint32_t RESERVED0[2U];
682 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
683 uint32_t RESERVED1[55U];
684 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
685 uint32_t RESERVED2[131U];
686 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
687 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
688 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
689 uint32_t RESERVED3[759U];
690 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
691 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
692 __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
693 uint32_t RESERVED4[1U];
694 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
695 __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
696 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
697 uint32_t RESERVED5[39U];
698 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
699 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
700 uint32_t RESERVED7[8U];
701 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
702 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
703 } TPIU_Type;
704
705 /** \brief TPIU Asynchronous Clock Prescaler Register Definitions */
706 #define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */
707 #define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */
708
709 /** \brief TPIU Selected Pin Protocol Register Definitions */
710 #define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */
711 #define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */
712
713 /** \brief TPIU Formatter and Flush Status Register Definitions */
714 #define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */
715 #define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */
716
717 #define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */
718 #define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */
719
720 #define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */
721 #define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */
722
723 #define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */
724 #define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */
725
726 /** \brief TPIU Formatter and Flush Control Register Definitions */
727 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */
728 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */
729
730 #define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */
731 #define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */
732
733 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */
734 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
735
736 /** \brief TPIU Periodic Synchronization Control Register Definitions */
737 #define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */
738 #define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */
739
740 /** \brief TPIU TRIGGER Register Definitions */
741 #define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */
742 #define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */
743
744 /** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */
745 #define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */
746 #define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */
747
748 #define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */
749 #define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */
750
751 #define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */
752 #define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */
753
754 #define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */
755 #define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */
756
757 #define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */
758 #define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */
759
760 #define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */
761 #define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */
762
763 #define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */
764 #define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */
765
766 /** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */
767 #define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */
768 #define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */
769
770 #define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */
771 #define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */
772
773 #define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */
774 #define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */
775
776 #define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */
777 #define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */
778
779 /** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */
780 #define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */
781 #define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */
782
783 #define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */
784 #define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */
785
786 #define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */
787 #define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */
788
789 #define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */
790 #define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */
791
792 #define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */
793 #define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */
794
795 #define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */
796 #define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */
797
798 #define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */
799 #define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */
800
801 /** \brief TPIU Integration Test ATB Control Register 0 Definitions */
802 #define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */
803 #define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */
804
805 #define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */
806 #define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */
807
808 #define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */
809 #define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */
810
811 #define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */
812 #define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */
813
814 /** \brief TPIU Integration Mode Control Register Definitions */
815 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */
816 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
817
818 /** \brief TPIU DEVID Register Definitions */
819 #define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */
820 #define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */
821
822 #define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */
823 #define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */
824
825 #define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */
826 #define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */
827
828 #define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */
829 #define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */
830
831 #define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */
832 #define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */
833
834 /** \brief TPIU DEVTYPE Register Definitions */
835 #define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */
836 #define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */
837
838 #define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */
839 #define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */
840
841 /*@}*/ /* end of group CMSIS_TPIU */
842
843
844 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
845 /**
846 \ingroup CMSIS_core_register
847 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
848 \brief Type definitions for the Memory Protection Unit (MPU)
849 @{
850 */
851
852 /**
853 \brief Structure type to access the Memory Protection Unit (MPU).
854 */
855 typedef struct
856 {
857 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
858 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
859 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
860 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
861 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
862 uint32_t RESERVED0[7U];
863 union {
864 __IOM uint32_t MAIR[2];
865 struct {
866 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
867 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
868 };
869 };
870 } MPU_Type;
871
872 #define MPU_TYPE_RALIASES 1U
873
874 /** \brief MPU Type Register Definitions */
875 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
876 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
877
878 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
879 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
880
881 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
882 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
883
884 /** \brief MPU Control Register Definitions */
885 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
886 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
887
888 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
889 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
890
891 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
892 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
893
894 /** \brief MPU Region Number Register Definitions */
895 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
896 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
897
898 /** \brief MPU Region Base Address Register Definitions */
899 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
900 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
901
902 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
903 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
904
905 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
906 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
907
908 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
909 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
910
911 /** \brief MPU Region Limit Address Register Definitions */
912 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
913 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
914
915 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
916 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
917
918 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
919 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */
920
921 /** \brief MPU Memory Attribute Indirection Register 0 Definitions */
922 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
923 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
924
925 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
926 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
927
928 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
929 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
930
931 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
932 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
933
934 /** \brief MPU Memory Attribute Indirection Register 1 Definitions */
935 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
936 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
937
938 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
939 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
940
941 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
942 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
943
944 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
945 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
946
947 /*@} end of group CMSIS_MPU */
948 #endif
949
950
951 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
952 /**
953 \ingroup CMSIS_core_register
954 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
955 \brief Type definitions for the Security Attribution Unit (SAU)
956 @{
957 */
958
959 /**
960 \brief Structure type to access the Security Attribution Unit (SAU).
961 */
962 typedef struct
963 {
964 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
965 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
966 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
967 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
968 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
969 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
970 #endif
971 } SAU_Type;
972
973 /** \brief SAU Control Register Definitions */
974 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
975 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
976
977 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
978 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
979
980 /** \brief SAU Type Register Definitions */
981 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
982 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
983
984 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
985 /** \brief SAU Region Number Register Definitions */
986 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
987 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
988
989 /** \brief SAU Region Base Address Register Definitions */
990 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
991 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
992
993 /** \brief SAU Region Limit Address Register Definitions */
994 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
995 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
996
997 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
998 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
999
1000 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1001 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1002
1003 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1004
1005 /*@} end of group CMSIS_SAU */
1006 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1007
1008
1009
1010 /**
1011 \ingroup CMSIS_core_register
1012 \defgroup CMSIS_DCB Debug Control Block
1013 \brief Type definitions for the Debug Control Block Registers
1014 @{
1015 */
1016
1017 /**
1018 \brief Structure type to access the Debug Control Block Registers (DCB).
1019 */
1020 typedef struct
1021 {
1022 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1023 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1024 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1025 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1026 uint32_t RESERVED0[1U];
1027 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1028 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1029 } DCB_Type;
1030
1031 /** \brief DCB Debug Halting Control and Status Register Definitions */
1032 #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
1033 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
1034
1035 #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
1036 #define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
1037
1038 #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
1039 #define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
1040
1041 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
1042 #define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
1043
1044 #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
1045 #define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
1046
1047 #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
1048 #define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
1049
1050 #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
1051 #define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
1052
1053 #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
1054 #define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
1055
1056 #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
1057 #define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
1058
1059 #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
1060 #define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
1061
1062 #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
1063 #define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
1064
1065 #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
1066 #define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
1067
1068 #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
1069 #define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
1070
1071 /** \brief DCB Debug Core Register Selector Register Definitions */
1072 #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
1073 #define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
1074
1075 #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
1076 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
1077
1078 /** \brief DCB Debug Core Register Data Register Definitions */
1079 #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
1080 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
1081
1082 /** \brief DCB Debug Exception and Monitor Control Register Definitions */
1083 #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
1084 #define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
1085
1086 #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
1087 #define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
1088
1089 #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
1090 #define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
1091
1092 /** \brief DCB Debug Authentication Control Register Definitions */
1093 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
1094 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
1095
1096 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
1097 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
1098
1099 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
1100 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
1101
1102 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
1103 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
1104
1105 /** \brief DCB Debug Security Control and Status Register Definitions */
1106 #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
1107 #define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
1108
1109 #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
1110 #define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
1111
1112 #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
1113 #define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
1114
1115 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
1116 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
1117
1118 /*@} end of group CMSIS_DCB */
1119
1120
1121 /**
1122 \ingroup CMSIS_core_register
1123 \defgroup CMSIS_DIB Debug Identification Block
1124 \brief Type definitions for the Debug Identification Block Registers
1125 @{
1126 */
1127
1128 /**
1129 \brief Structure type to access the Debug Identification Block Registers (DIB).
1130 */
1131 typedef struct
1132 {
1133 __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
1134 __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
1135 __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
1136 __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
1137 __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
1138 } DIB_Type;
1139
1140 /** \brief DIB SCS Software Lock Access Register Definitions */
1141 #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
1142 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
1143
1144 /** \brief DIB SCS Software Lock Status Register Definitions */
1145 #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
1146 #define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
1147
1148 #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
1149 #define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
1150
1151 #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
1152 #define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
1153
1154 /** \brief DIB Debug Authentication Status Register Definitions */
1155 #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
1156 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
1157
1158 #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
1159 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
1160
1161 #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
1162 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
1163
1164 #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
1165 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
1166
1167 /** \brief DIB SCS Device Architecture Register Definitions */
1168 #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
1169 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
1170
1171 #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
1172 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
1173
1174 #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
1175 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
1176
1177 #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
1178 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
1179
1180 #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
1181 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
1182
1183 /** \brief DIB SCS Device Type Register Definitions */
1184 #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
1185 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
1186
1187 #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
1188 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
1189
1190 /*@} end of group CMSIS_DIB */
1191
1192
1193 /**
1194 \ingroup CMSIS_core_register
1195 \defgroup CMSIS_core_bitfield Core register bit field macros
1196 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1197 @{
1198 */
1199
1200 /**
1201 \brief Mask and shift a bit field value for use in a register bit range.
1202 \param[in] field Name of the register bit field.
1203 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1204 \return Masked and shifted value.
1205 */
1206 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1207
1208 /**
1209 \brief Mask and shift a register value to extract a bit field value.
1210 \param[in] field Name of the register bit field.
1211 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1212 \return Masked and shifted bit field value.
1213 */
1214 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1215
1216 /*@} end of group CMSIS_core_bitfield */
1217
1218
1219 /**
1220 \ingroup CMSIS_core_register
1221 \defgroup CMSIS_core_base Core Definitions
1222 \brief Definitions for base addresses, unions, and structures.
1223 @{
1224 */
1225
1226 /* Memory mapping of Core Hardware */
1227 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1228 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1229 #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */
1230 #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
1231 #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
1232 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1233 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1234 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1235
1236
1237 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1238 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1239 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1240 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1241 #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */
1242 #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
1243 #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
1244
1245 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1246 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1247 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1248 #endif
1249
1250 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1251 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
1252 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
1253 #endif
1254
1255 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1256 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
1257 #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
1258 #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
1259 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
1260 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
1261 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
1262
1263 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
1264 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
1265 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
1266 #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
1267 #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
1268
1269 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1270 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
1271 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
1272 #endif
1273
1274 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1275 /*@} */
1276
1277
1278 /**
1279 \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases
1280 \brief Alias definitions present for backwards compatibility for deprecated symbols.
1281 @{
1282 */
1283
1284 #ifndef CMSIS_DISABLE_DEPRECATED
1285
1286 #define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
1287 #define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk
1288
1289 /* deprecated, CMSIS_5 backward compatibility */
1290 typedef struct
1291 {
1292 __IOM uint32_t DHCSR;
1293 __OM uint32_t DCRSR;
1294 __IOM uint32_t DCRDR;
1295 __IOM uint32_t DEMCR;
1296 uint32_t RESERVED0[1U];
1297 __IOM uint32_t DAUTHCTRL;
1298 __IOM uint32_t DSCSR;
1299 } CoreDebug_Type;
1300
1301 /* Debug Halting Control and Status Register Definitions */
1302 #define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos
1303 #define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk
1304
1305 #define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos
1306 #define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk
1307
1308 #define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos
1309 #define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk
1310
1311 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos
1312 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk
1313
1314 #define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos
1315 #define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk
1316
1317 #define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos
1318 #define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk
1319
1320 #define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos
1321 #define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk
1322
1323 #define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos
1324 #define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk
1325
1326 #define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos
1327 #define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk
1328
1329 #define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos
1330 #define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk
1331
1332 #define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos
1333 #define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk
1334
1335 #define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos
1336 #define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk
1337
1338 /* Debug Core Register Selector Register Definitions */
1339 #define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos
1340 #define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk
1341
1342 #define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos
1343 #define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk
1344
1345 /* Debug Exception and Monitor Control Register Definitions */
1346 #define CoreDebug_DEMCR_DWTENA_Pos DCB_DEMCR_TRCENA_Pos
1347 #define CoreDebug_DEMCR_DWTENA_Msk DCB_DEMCR_TRCENA_Msk
1348
1349 #define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos
1350 #define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk
1351
1352 #define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos
1353 #define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk
1354
1355 /* Debug Authentication Control Register Definitions */
1356 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos
1357 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk
1358
1359 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos
1360 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk
1361
1362 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos
1363 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk
1364
1365 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos
1366 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk
1367
1368 /* Debug Security Control and Status Register Definitions */
1369 #define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos
1370 #define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk
1371
1372 #define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos
1373 #define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk
1374
1375 #define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos
1376 #define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk
1377
1378 #define CoreDebug ((CoreDebug_Type *) DCB_BASE)
1379 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1380 #define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS)
1381 #endif
1382
1383 #endif // CMSIS_DISABLE_DEPRECATED
1384
1385 /*@} */
1386
1387
1388 /*******************************************************************************
1389 * Hardware Abstraction Layer
1390 Core Function Interface contains:
1391 - Core NVIC Functions
1392 - Core SysTick Functions
1393 - Core Debug Functions
1394 - Core Register Access Functions
1395 ******************************************************************************/
1396 /**
1397 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1398 */
1399
1400
1401
1402 /* ########################## NVIC functions #################################### */
1403 /**
1404 \ingroup CMSIS_Core_FunctionInterface
1405 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1406 \brief Functions that manage interrupts and exceptions via the NVIC.
1407 @{
1408 */
1409
1410 #ifdef CMSIS_NVIC_VIRTUAL
1411 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1412 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1413 #endif
1414 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1415 #else
1416 /* NVIC_SetPriorityGrouping not available for Cortex-M23 */
1417 /* NVIC_GetPriorityGrouping not available for Cortex-M23 */
1418 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1419 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1420 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1421 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1422 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1423 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1424 #define NVIC_GetActive __NVIC_GetActive
1425 #define NVIC_SetPriority __NVIC_SetPriority
1426 #define NVIC_GetPriority __NVIC_GetPriority
1427 #define NVIC_SystemReset __NVIC_SystemReset
1428 #endif /* CMSIS_NVIC_VIRTUAL */
1429
1430 #ifdef CMSIS_VECTAB_VIRTUAL
1431 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1432 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1433 #endif
1434 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1435 #else
1436 #define NVIC_SetVector __NVIC_SetVector
1437 #define NVIC_GetVector __NVIC_GetVector
1438 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1439
1440 #define NVIC_USER_IRQ_OFFSET 16
1441
1442
1443 /* Special LR values for Secure/Non-Secure call handling and exception handling */
1444
1445 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
1446 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
1447
1448 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
1449 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
1450 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
1451 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
1452 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
1453 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
1454 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
1455 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
1456
1457 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
1458 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
1459 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
1460 #else
1461 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
1462 #endif
1463
1464
1465 /* Interrupt Priorities are WORD accessible only under Armv6-M */
1466 /* The following MACROS handle generation of the register offset and byte masks */
1467 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
1468 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
1469 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
1470
1471 #define __NVIC_SetPriorityGrouping(X) (void)(X)
1472 #define __NVIC_GetPriorityGrouping() (0U)
1473
1474 /**
1475 \brief Enable Interrupt
1476 \details Enables a device specific interrupt in the NVIC interrupt controller.
1477 \param [in] IRQn Device specific interrupt number.
1478 \note IRQn must not be negative.
1479 */
__NVIC_EnableIRQ(IRQn_Type IRQn)1480 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1481 {
1482 if ((int32_t)(IRQn) >= 0)
1483 {
1484 __COMPILER_BARRIER();
1485 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1486 __COMPILER_BARRIER();
1487 }
1488 }
1489
1490
1491 /**
1492 \brief Get Interrupt Enable status
1493 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1494 \param [in] IRQn Device specific interrupt number.
1495 \return 0 Interrupt is not enabled.
1496 \return 1 Interrupt is enabled.
1497 \note IRQn must not be negative.
1498 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)1499 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1500 {
1501 if ((int32_t)(IRQn) >= 0)
1502 {
1503 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1504 }
1505 else
1506 {
1507 return(0U);
1508 }
1509 }
1510
1511
1512 /**
1513 \brief Disable Interrupt
1514 \details Disables a device specific interrupt in the NVIC interrupt controller.
1515 \param [in] IRQn Device specific interrupt number.
1516 \note IRQn must not be negative.
1517 */
__NVIC_DisableIRQ(IRQn_Type IRQn)1518 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1519 {
1520 if ((int32_t)(IRQn) >= 0)
1521 {
1522 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1523 __DSB();
1524 __ISB();
1525 }
1526 }
1527
1528
1529 /**
1530 \brief Get Pending Interrupt
1531 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1532 \param [in] IRQn Device specific interrupt number.
1533 \return 0 Interrupt status is not pending.
1534 \return 1 Interrupt status is pending.
1535 \note IRQn must not be negative.
1536 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)1537 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1538 {
1539 if ((int32_t)(IRQn) >= 0)
1540 {
1541 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1542 }
1543 else
1544 {
1545 return(0U);
1546 }
1547 }
1548
1549
1550 /**
1551 \brief Set Pending Interrupt
1552 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1553 \param [in] IRQn Device specific interrupt number.
1554 \note IRQn must not be negative.
1555 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)1556 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1557 {
1558 if ((int32_t)(IRQn) >= 0)
1559 {
1560 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1561 }
1562 }
1563
1564
1565 /**
1566 \brief Clear Pending Interrupt
1567 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1568 \param [in] IRQn Device specific interrupt number.
1569 \note IRQn must not be negative.
1570 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)1571 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1572 {
1573 if ((int32_t)(IRQn) >= 0)
1574 {
1575 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1576 }
1577 }
1578
1579
1580 /**
1581 \brief Get Active Interrupt
1582 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1583 \param [in] IRQn Device specific interrupt number.
1584 \return 0 Interrupt status is not active.
1585 \return 1 Interrupt status is active.
1586 \note IRQn must not be negative.
1587 */
__NVIC_GetActive(IRQn_Type IRQn)1588 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1589 {
1590 if ((int32_t)(IRQn) >= 0)
1591 {
1592 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1593 }
1594 else
1595 {
1596 return(0U);
1597 }
1598 }
1599
1600
1601 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1602 /**
1603 \brief Get Interrupt Target State
1604 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1605 \param [in] IRQn Device specific interrupt number.
1606 \return 0 if interrupt is assigned to Secure
1607 \return 1 if interrupt is assigned to Non Secure
1608 \note IRQn must not be negative.
1609 */
NVIC_GetTargetState(IRQn_Type IRQn)1610 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
1611 {
1612 if ((int32_t)(IRQn) >= 0)
1613 {
1614 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1615 }
1616 else
1617 {
1618 return(0U);
1619 }
1620 }
1621
1622
1623 /**
1624 \brief Set Interrupt Target State
1625 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1626 \param [in] IRQn Device specific interrupt number.
1627 \return 0 if interrupt is assigned to Secure
1628 1 if interrupt is assigned to Non Secure
1629 \note IRQn must not be negative.
1630 */
NVIC_SetTargetState(IRQn_Type IRQn)1631 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
1632 {
1633 if ((int32_t)(IRQn) >= 0)
1634 {
1635 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1636 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1637 }
1638 else
1639 {
1640 return(0U);
1641 }
1642 }
1643
1644
1645 /**
1646 \brief Clear Interrupt Target State
1647 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1648 \param [in] IRQn Device specific interrupt number.
1649 \return 0 if interrupt is assigned to Secure
1650 1 if interrupt is assigned to Non Secure
1651 \note IRQn must not be negative.
1652 */
NVIC_ClearTargetState(IRQn_Type IRQn)1653 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
1654 {
1655 if ((int32_t)(IRQn) >= 0)
1656 {
1657 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1658 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1659 }
1660 else
1661 {
1662 return(0U);
1663 }
1664 }
1665 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1666
1667
1668 /**
1669 \brief Set Interrupt Priority
1670 \details Sets the priority of a device specific interrupt or a processor exception.
1671 The interrupt number can be positive to specify a device specific interrupt,
1672 or negative to specify a processor exception.
1673 \param [in] IRQn Interrupt number.
1674 \param [in] priority Priority to set.
1675 \note The priority cannot be set for every processor exception.
1676 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)1677 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1678 {
1679 if ((int32_t)(IRQn) >= 0)
1680 {
1681 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1682 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1683 }
1684 else
1685 {
1686 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1687 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1688 }
1689 }
1690
1691
1692 /**
1693 \brief Get Interrupt Priority
1694 \details Reads the priority of a device specific interrupt or a processor exception.
1695 The interrupt number can be positive to specify a device specific interrupt,
1696 or negative to specify a processor exception.
1697 \param [in] IRQn Interrupt number.
1698 \return Interrupt Priority.
1699 Value is aligned automatically to the implemented priority bits of the microcontroller.
1700 */
__NVIC_GetPriority(IRQn_Type IRQn)1701 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1702 {
1703
1704 if ((int32_t)(IRQn) >= 0)
1705 {
1706 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1707 }
1708 else
1709 {
1710 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1711 }
1712 }
1713
1714
1715 /**
1716 \brief Encode Priority
1717 \details Encodes the priority for an interrupt with the given priority group,
1718 preemptive priority value, and subpriority value.
1719 In case of a conflict between priority grouping and available
1720 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1721 \param [in] PriorityGroup Used priority group.
1722 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1723 \param [in] SubPriority Subpriority value (starting from 0).
1724 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1725 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)1726 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1727 {
1728 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1729 uint32_t PreemptPriorityBits;
1730 uint32_t SubPriorityBits;
1731
1732 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1733 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1734
1735 return (
1736 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1737 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1738 );
1739 }
1740
1741
1742 /**
1743 \brief Decode Priority
1744 \details Decodes an interrupt priority value with a given priority group to
1745 preemptive priority value and subpriority value.
1746 In case of a conflict between priority grouping and available
1747 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1748 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1749 \param [in] PriorityGroup Used priority group.
1750 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1751 \param [out] pSubPriority Subpriority value (starting from 0).
1752 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)1753 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1754 {
1755 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1756 uint32_t PreemptPriorityBits;
1757 uint32_t SubPriorityBits;
1758
1759 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1760 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1761
1762 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1763 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1764 }
1765
1766
1767 /**
1768 \brief Set Interrupt Vector
1769 \details Sets an interrupt vector in SRAM based interrupt vector table.
1770 The interrupt number can be positive to specify a device specific interrupt,
1771 or negative to specify a processor exception.
1772 VTOR must been relocated to SRAM before.
1773 If VTOR is not present address 0 must be mapped to SRAM.
1774 \param [in] IRQn Interrupt number
1775 \param [in] vector Address of interrupt handler function
1776 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)1777 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1778 {
1779 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1780 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
1781 #else
1782 uint32_t *vectors = (uint32_t *)0x0U;
1783 #endif
1784 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1785 __DSB();
1786 }
1787
1788
1789 /**
1790 \brief Get Interrupt Vector
1791 \details Reads an interrupt vector from interrupt vector table.
1792 The interrupt number can be positive to specify a device specific interrupt,
1793 or negative to specify a processor exception.
1794 \param [in] IRQn Interrupt number.
1795 \return Address of interrupt handler function
1796 */
__NVIC_GetVector(IRQn_Type IRQn)1797 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1798 {
1799 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1800 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
1801 #else
1802 uint32_t *vectors = (uint32_t *)0x0U;
1803 #endif
1804 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1805 }
1806
1807
1808 /**
1809 \brief System Reset
1810 \details Initiates a system reset request to reset the MCU.
1811 */
__NVIC_SystemReset(void)1812 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1813 {
1814 __DSB(); /* Ensure all outstanding memory accesses included
1815 buffered write are completed before reset */
1816 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1817 SCB_AIRCR_SYSRESETREQ_Msk);
1818 __DSB(); /* Ensure completion of memory access */
1819
1820 for(;;) /* wait until reset */
1821 {
1822 __NOP();
1823 }
1824 }
1825
1826 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1827 /**
1828 \brief Enable Interrupt (non-secure)
1829 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
1830 \param [in] IRQn Device specific interrupt number.
1831 \note IRQn must not be negative.
1832 */
TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)1833 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
1834 {
1835 if ((int32_t)(IRQn) >= 0)
1836 {
1837 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1838 }
1839 }
1840
1841
1842 /**
1843 \brief Get Interrupt Enable status (non-secure)
1844 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
1845 \param [in] IRQn Device specific interrupt number.
1846 \return 0 Interrupt is not enabled.
1847 \return 1 Interrupt is enabled.
1848 \note IRQn must not be negative.
1849 */
TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)1850 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
1851 {
1852 if ((int32_t)(IRQn) >= 0)
1853 {
1854 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1855 }
1856 else
1857 {
1858 return(0U);
1859 }
1860 }
1861
1862
1863 /**
1864 \brief Disable Interrupt (non-secure)
1865 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
1866 \param [in] IRQn Device specific interrupt number.
1867 \note IRQn must not be negative.
1868 */
TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)1869 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
1870 {
1871 if ((int32_t)(IRQn) >= 0)
1872 {
1873 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1874 }
1875 }
1876
1877
1878 /**
1879 \brief Get Pending Interrupt (non-secure)
1880 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
1881 \param [in] IRQn Device specific interrupt number.
1882 \return 0 Interrupt status is not pending.
1883 \return 1 Interrupt status is pending.
1884 \note IRQn must not be negative.
1885 */
TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)1886 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
1887 {
1888 if ((int32_t)(IRQn) >= 0)
1889 {
1890 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1891 }
1892 else
1893 {
1894 return(0U);
1895 }
1896 }
1897
1898
1899 /**
1900 \brief Set Pending Interrupt (non-secure)
1901 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
1902 \param [in] IRQn Device specific interrupt number.
1903 \note IRQn must not be negative.
1904 */
TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)1905 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
1906 {
1907 if ((int32_t)(IRQn) >= 0)
1908 {
1909 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1910 }
1911 }
1912
1913
1914 /**
1915 \brief Clear Pending Interrupt (non-secure)
1916 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
1917 \param [in] IRQn Device specific interrupt number.
1918 \note IRQn must not be negative.
1919 */
TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)1920 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
1921 {
1922 if ((int32_t)(IRQn) >= 0)
1923 {
1924 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1925 }
1926 }
1927
1928
1929 /**
1930 \brief Get Active Interrupt (non-secure)
1931 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
1932 \param [in] IRQn Device specific interrupt number.
1933 \return 0 Interrupt status is not active.
1934 \return 1 Interrupt status is active.
1935 \note IRQn must not be negative.
1936 */
TZ_NVIC_GetActive_NS(IRQn_Type IRQn)1937 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
1938 {
1939 if ((int32_t)(IRQn) >= 0)
1940 {
1941 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1942 }
1943 else
1944 {
1945 return(0U);
1946 }
1947 }
1948
1949
1950 /**
1951 \brief Set Interrupt Priority (non-secure)
1952 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
1953 The interrupt number can be positive to specify a device specific interrupt,
1954 or negative to specify a processor exception.
1955 \param [in] IRQn Interrupt number.
1956 \param [in] priority Priority to set.
1957 \note The priority cannot be set for every non-secure processor exception.
1958 */
TZ_NVIC_SetPriority_NS(IRQn_Type IRQn,uint32_t priority)1959 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
1960 {
1961 if ((int32_t)(IRQn) >= 0)
1962 {
1963 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1964 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1965 }
1966 else
1967 {
1968 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1969 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1970 }
1971 }
1972
1973
1974 /**
1975 \brief Get Interrupt Priority (non-secure)
1976 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
1977 The interrupt number can be positive to specify a device specific interrupt,
1978 or negative to specify a processor exception.
1979 \param [in] IRQn Interrupt number.
1980 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
1981 */
TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)1982 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
1983 {
1984
1985 if ((int32_t)(IRQn) >= 0)
1986 {
1987 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1988 }
1989 else
1990 {
1991 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1992 }
1993 }
1994 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
1995
1996 /*@} end of CMSIS_Core_NVICFunctions */
1997
1998 /* ########################## MPU functions #################################### */
1999
2000 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2001
2002 #include "m-profile/armv8m_mpu.h"
2003
2004 #endif
2005
2006
2007 /* ########################## FPU functions #################################### */
2008 /**
2009 \ingroup CMSIS_Core_FunctionInterface
2010 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2011 \brief Function that provides FPU type.
2012 @{
2013 */
2014
2015 /**
2016 \brief get FPU type
2017 \details returns the FPU type
2018 \returns
2019 - \b 0: No FPU
2020 - \b 1: Single precision FPU
2021 - \b 2: Double + Single precision FPU
2022 */
SCB_GetFPUType(void)2023 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2024 {
2025 return 0U; /* No FPU */
2026 }
2027
2028 /*@} end of CMSIS_Core_FpuFunctions */
2029
2030
2031
2032 /* ########################## SAU functions #################################### */
2033 /**
2034 \ingroup CMSIS_Core_FunctionInterface
2035 \defgroup CMSIS_Core_SAUFunctions SAU Functions
2036 \brief Functions that configure the SAU.
2037 @{
2038 */
2039
2040 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2041
2042 /**
2043 \brief Enable SAU
2044 \details Enables the Security Attribution Unit (SAU).
2045 */
TZ_SAU_Enable(void)2046 __STATIC_INLINE void TZ_SAU_Enable(void)
2047 {
2048 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2049 }
2050
2051
2052
2053 /**
2054 \brief Disable SAU
2055 \details Disables the Security Attribution Unit (SAU).
2056 */
TZ_SAU_Disable(void)2057 __STATIC_INLINE void TZ_SAU_Disable(void)
2058 {
2059 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2060 }
2061
2062 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2063
2064 /*@} end of CMSIS_Core_SAUFunctions */
2065
2066
2067
2068
2069 /* ################################## Debug Control function ############################################ */
2070 /**
2071 \ingroup CMSIS_Core_FunctionInterface
2072 \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
2073 \brief Functions that access the Debug Control Block.
2074 @{
2075 */
2076
2077
2078 /**
2079 \brief Set Debug Authentication Control Register
2080 \details writes to Debug Authentication Control register.
2081 \param [in] value value to be writen.
2082 */
DCB_SetAuthCtrl(uint32_t value)2083 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
2084 {
2085 __DSB();
2086 __ISB();
2087 DCB->DAUTHCTRL = value;
2088 __DSB();
2089 __ISB();
2090 }
2091
2092
2093 /**
2094 \brief Get Debug Authentication Control Register
2095 \details Reads Debug Authentication Control register.
2096 \return Debug Authentication Control Register.
2097 */
DCB_GetAuthCtrl(void)2098 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
2099 {
2100 return (DCB->DAUTHCTRL);
2101 }
2102
2103
2104 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2105 /**
2106 \brief Set Debug Authentication Control Register (non-secure)
2107 \details writes to non-secure Debug Authentication Control register when in secure state.
2108 \param [in] value value to be writen
2109 */
TZ_DCB_SetAuthCtrl_NS(uint32_t value)2110 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
2111 {
2112 __DSB();
2113 __ISB();
2114 DCB_NS->DAUTHCTRL = value;
2115 __DSB();
2116 __ISB();
2117 }
2118
2119
2120 /**
2121 \brief Get Debug Authentication Control Register (non-secure)
2122 \details Reads non-secure Debug Authentication Control register when in secure state.
2123 \return Debug Authentication Control Register.
2124 */
TZ_DCB_GetAuthCtrl_NS(void)2125 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
2126 {
2127 return (DCB_NS->DAUTHCTRL);
2128 }
2129 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2130
2131 /*@} end of CMSIS_Core_DCBFunctions */
2132
2133
2134
2135
2136 /* ################################## Debug Identification function ############################################ */
2137 /**
2138 \ingroup CMSIS_Core_FunctionInterface
2139 \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
2140 \brief Functions that access the Debug Identification Block.
2141 @{
2142 */
2143
2144
2145 /**
2146 \brief Get Debug Authentication Status Register
2147 \details Reads Debug Authentication Status register.
2148 \return Debug Authentication Status Register.
2149 */
DIB_GetAuthStatus(void)2150 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
2151 {
2152 return (DIB->DAUTHSTATUS);
2153 }
2154
2155
2156 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2157 /**
2158 \brief Get Debug Authentication Status Register (non-secure)
2159 \details Reads non-secure Debug Authentication Status register when in secure state.
2160 \return Debug Authentication Status Register.
2161 */
TZ_DIB_GetAuthStatus_NS(void)2162 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
2163 {
2164 return (DIB_NS->DAUTHSTATUS);
2165 }
2166 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2167
2168 /*@} end of CMSIS_Core_DCBFunctions */
2169
2170
2171
2172
2173 /* ################################## SysTick function ############################################ */
2174 /**
2175 \ingroup CMSIS_Core_FunctionInterface
2176 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2177 \brief Functions that configure the System.
2178 @{
2179 */
2180
2181 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2182
2183 /**
2184 \brief System Tick Configuration
2185 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2186 Counter is in free running mode to generate periodic interrupts.
2187 \param [in] ticks Number of ticks between two interrupts.
2188 \return 0 Function succeeded.
2189 \return 1 Function failed.
2190 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2191 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2192 must contain a vendor-specific implementation of this function.
2193 */
SysTick_Config(uint32_t ticks)2194 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2195 {
2196 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2197 {
2198 return (1UL); /* Reload value impossible */
2199 }
2200
2201 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2202 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2203 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2204 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2205 SysTick_CTRL_TICKINT_Msk |
2206 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2207 return (0UL); /* Function successful */
2208 }
2209
2210 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2211 /**
2212 \brief System Tick Configuration (non-secure)
2213 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
2214 Counter is in free running mode to generate periodic interrupts.
2215 \param [in] ticks Number of ticks between two interrupts.
2216 \return 0 Function succeeded.
2217 \return 1 Function failed.
2218 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2219 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
2220 must contain a vendor-specific implementation of this function.
2221
2222 */
TZ_SysTick_Config_NS(uint32_t ticks)2223 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
2224 {
2225 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2226 {
2227 return (1UL); /* Reload value impossible */
2228 }
2229
2230 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2231 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2232 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
2233 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2234 SysTick_CTRL_TICKINT_Msk |
2235 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2236 return (0UL); /* Function successful */
2237 }
2238 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2239
2240 #endif
2241
2242 /*@} end of CMSIS_Core_SysTickFunctions */
2243
2244
2245
2246
2247 #ifdef __cplusplus
2248 }
2249 #endif
2250
2251 #endif /* __CORE_CM23_H_DEPENDANT */
2252
2253 #endif /* __CMSIS_GENERIC */
2254
