1 /*
2 * Copyright (c) 2009-2024 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * CMSIS Cortex-M7 Core Peripheral Access Layer Header File
21 */
22
23 #if defined ( __ICCARM__ )
24 #pragma system_include /* treat file as system include file for MISRA check */
25 #elif defined (__clang__)
26 #pragma clang system_header /* treat file as system include file */
27 #elif defined ( __GNUC__ )
28 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
29 #endif
30
31 #ifndef __CORE_CM7_H_GENERIC
32 #define __CORE_CM7_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup Cortex_M7
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS CM7 definitions */
66
67 #define __CORTEX_M (7U) /*!< Cortex-M Core */
68
69 /** __FPU_USED indicates whether an FPU is used or not.
70 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
71 */
72 #if defined ( __CC_ARM )
73 #if defined (__TARGET_FPU_VFP)
74 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
75 #define __FPU_USED 1U
76 #else
77 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
78 #define __FPU_USED 0U
79 #endif
80 #else
81 #define __FPU_USED 0U
82 #endif
83
84 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
85 #if defined (__ARM_FP)
86 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
87 #define __FPU_USED 1U
88 #else
89 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
90 #define __FPU_USED 0U
91 #endif
92 #else
93 #define __FPU_USED 0U
94 #endif
95
96 #elif defined (__ti__)
97 #if defined (__ARM_FP)
98 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
99 #define __FPU_USED 1U
100 #else
101 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
102 #define __FPU_USED 0U
103 #endif
104 #else
105 #define __FPU_USED 0U
106 #endif
107
108 #elif defined ( __GNUC__ )
109 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
110 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
111 #define __FPU_USED 1U
112 #else
113 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
114 #define __FPU_USED 0U
115 #endif
116 #else
117 #define __FPU_USED 0U
118 #endif
119
120 #elif defined ( __ICCARM__ )
121 #if defined (__ARMVFP__)
122 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
123 #define __FPU_USED 1U
124 #else
125 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
126 #define __FPU_USED 0U
127 #endif
128 #else
129 #define __FPU_USED 0U
130 #endif
131
132 #elif defined ( __TI_ARM__ )
133 #if defined (__TI_VFP_SUPPORT__)
134 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
135 #define __FPU_USED 1U
136 #else
137 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
138 #define __FPU_USED 0U
139 #endif
140 #else
141 #define __FPU_USED 0U
142 #endif
143
144 #elif defined ( __TASKING__ )
145 #if defined (__FPU_VFP__)
146 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
147 #define __FPU_USED 1U
148 #else
149 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
150 #define __FPU_USED 0U
151 #endif
152 #else
153 #define __FPU_USED 0U
154 #endif
155
156 #elif defined ( __CSMC__ )
157 #if ( __CSMC__ & 0x400U)
158 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
159 #define __FPU_USED 1U
160 #else
161 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
162 #define __FPU_USED 0U
163 #endif
164 #else
165 #define __FPU_USED 0U
166 #endif
167
168 #endif
169
170 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
171
172
173 #ifdef __cplusplus
174 }
175 #endif
176
177 #endif /* __CORE_CM7_H_GENERIC */
178
179 #ifndef __CMSIS_GENERIC
180
181 #ifndef __CORE_CM7_H_DEPENDANT
182 #define __CORE_CM7_H_DEPENDANT
183
184 #ifdef __cplusplus
185 extern "C" {
186 #endif
187
188 /* check device defines and use defaults */
189 #if defined __CHECK_DEVICE_DEFINES
190 #ifndef __CM7_REV
191 #define __CM7_REV 0x0000U
192 #warning "__CM7_REV not defined in device header file; using default!"
193 #endif
194
195 #ifndef __FPU_PRESENT
196 #define __FPU_PRESENT 0U
197 #warning "__FPU_PRESENT not defined in device header file; using default!"
198 #endif
199
200 #ifndef __MPU_PRESENT
201 #define __MPU_PRESENT 0U
202 #warning "__MPU_PRESENT not defined in device header file; using default!"
203 #endif
204
205 #ifndef __ICACHE_PRESENT
206 #define __ICACHE_PRESENT 0U
207 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
208 #endif
209
210 #ifndef __DCACHE_PRESENT
211 #define __DCACHE_PRESENT 0U
212 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
213 #endif
214
215 #ifndef __DTCM_PRESENT
216 #define __DTCM_PRESENT 0U
217 #warning "__DTCM_PRESENT not defined in device header file; using default!"
218 #endif
219
220 #ifndef __VTOR_PRESENT
221 #define __VTOR_PRESENT 1U
222 #warning "__VTOR_PRESENT not defined in device header file; using default!"
223 #endif
224
225 #ifndef __NVIC_PRIO_BITS
226 #define __NVIC_PRIO_BITS 3U
227 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
228 #endif
229
230 #ifndef __Vendor_SysTickConfig
231 #define __Vendor_SysTickConfig 0U
232 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
233 #endif
234 #endif
235
236 /* IO definitions (access restrictions to peripheral registers) */
237 /**
238 \defgroup CMSIS_glob_defs CMSIS Global Defines
239
240 <strong>IO Type Qualifiers</strong> are used
241 \li to specify the access to peripheral variables.
242 \li for automatic generation of peripheral register debug information.
243 */
244 #ifdef __cplusplus
245 #define __I volatile /*!< Defines 'read only' permissions */
246 #else
247 #define __I volatile const /*!< Defines 'read only' permissions */
248 #endif
249 #define __O volatile /*!< Defines 'write only' permissions */
250 #define __IO volatile /*!< Defines 'read / write' permissions */
251
252 /* following defines should be used for structure members */
253 #define __IM volatile const /*! Defines 'read only' structure member permissions */
254 #define __OM volatile /*! Defines 'write only' structure member permissions */
255 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
256
257 /*@} end of group Cortex_M7 */
258
259
260
261 /*******************************************************************************
262 * Register Abstraction
263 Core Register contain:
264 - Core Register
265 - Core NVIC Register
266 - Core SCB Register
267 - Core SysTick Register
268 - Core Debug Register
269 - Core MPU Register
270 - Core FPU Register
271 ******************************************************************************/
272 /**
273 \defgroup CMSIS_core_register Defines and Type Definitions
274 \brief Type definitions and defines for Cortex-M processor based devices.
275 */
276
277 /**
278 \ingroup CMSIS_core_register
279 \defgroup CMSIS_CORE Status and Control Registers
280 \brief Core Register type definitions.
281 @{
282 */
283
284 /**
285 \brief Union type to access the Application Program Status Register (APSR).
286 */
287 typedef union
288 {
289 struct
290 {
291 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
292 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
293 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
294 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
295 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
296 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
297 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
298 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
299 } b; /*!< Structure used for bit access */
300 uint32_t w; /*!< Type used for word access */
301 } APSR_Type;
302
303 /** \brief APSR Register Definitions */
304 #define APSR_N_Pos 31U /*!< APSR: N Position */
305 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
306
307 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
308 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
309
310 #define APSR_C_Pos 29U /*!< APSR: C Position */
311 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
312
313 #define APSR_V_Pos 28U /*!< APSR: V Position */
314 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
315
316 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
317 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
318
319 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
320 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
321
322
323 /**
324 \brief Union type to access the Interrupt Program Status Register (IPSR).
325 */
326 typedef union
327 {
328 struct
329 {
330 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
331 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
332 } b; /*!< Structure used for bit access */
333 uint32_t w; /*!< Type used for word access */
334 } IPSR_Type;
335
336 /** \brief IPSR Register Definitions */
337 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
338 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
339
340
341 /**
342 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
343 */
344 typedef union
345 {
346 struct
347 {
348 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
349 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
350 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
351 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
352 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
353 uint32_t T:1; /*!< bit: 24 Thumb bit */
354 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
355 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
356 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
357 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
358 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
359 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
360 } b; /*!< Structure used for bit access */
361 uint32_t w; /*!< Type used for word access */
362 } xPSR_Type;
363
364 /** \brief xPSR Register Definitions */
365 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
366 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
367
368 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
369 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
370
371 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
372 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
373
374 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
375 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
376
377 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
378 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
379
380 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
381 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
382
383 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
384 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
385
386 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
387 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
388
389 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
390 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
391
392 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
393 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
394
395
396 /**
397 \brief Union type to access the Control Registers (CONTROL).
398 */
399 typedef union
400 {
401 struct
402 {
403 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
404 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
405 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
406 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
407 } b; /*!< Structure used for bit access */
408 uint32_t w; /*!< Type used for word access */
409 } CONTROL_Type;
410
411 /** \brief CONTROL Register Definitions */
412 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
413 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
414
415 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
416 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
417
418 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
419 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
420
421 /*@} end of group CMSIS_CORE */
422
423
424 /**
425 \ingroup CMSIS_core_register
426 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
427 \brief Type definitions for the NVIC Registers
428 @{
429 */
430
431 /**
432 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
433 */
434 typedef struct
435 {
436 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
437 uint32_t RESERVED0[24U];
438 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
439 uint32_t RESERVED1[24U];
440 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
441 uint32_t RESERVED2[24U];
442 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
443 uint32_t RESERVED3[24U];
444 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
445 uint32_t RESERVED4[56U];
446 __IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
447 uint32_t RESERVED5[644U];
448 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
449 } NVIC_Type;
450
451 /** \brief NVIC Software Triggered Interrupt Register Definitions */
452 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
453 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
454
455 /*@} end of group CMSIS_NVIC */
456
457
458 /**
459 \ingroup CMSIS_core_register
460 \defgroup CMSIS_SCB System Control Block (SCB)
461 \brief Type definitions for the System Control Block Registers
462 @{
463 */
464
465 /**
466 \brief Structure type to access the System Control Block (SCB).
467 */
468 typedef struct
469 {
470 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
471 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
472 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
473 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
474 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
475 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
476 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
477 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
478 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
479 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
480 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
481 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
482 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
483 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
484 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
485 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
486 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
487 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
488 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
489 uint32_t RESERVED0[1U];
490 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
491 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
492 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
493 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
494 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
495 uint32_t RESERVED3[93U];
496 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
497 uint32_t RESERVED4[15U];
498 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
499 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
500 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
501 uint32_t RESERVED5[1U];
502 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
503 uint32_t RESERVED6[1U];
504 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
505 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
506 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
507 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
508 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
509 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
510 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
511 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
512 __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
513 uint32_t RESERVED7[5U];
514 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
515 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
516 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
517 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
518 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
519 uint32_t RESERVED8[1U];
520 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
521 } SCB_Type;
522
523 /** \brief SCB CPUID Register Definitions */
524 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
525 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
526
527 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
528 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
529
530 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
531 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
532
533 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
534 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
535
536 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
537 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
538
539 /** \brief SCB Interrupt Control State Register Definitions */
540 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
541 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
542
543 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
544 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
545
546 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
547 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
548
549 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
550 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
551
552 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
553 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
554
555 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
556 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
557
558 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
559 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
560
561 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
562 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
563
564 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
565 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
566
567 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
568 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
569
570 /** \brief SCB Vector Table Offset Register Definitions */
571 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
572 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
573
574 /** \brief SCB Application Interrupt and Reset Control Register Definitions */
575 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
576 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
577
578 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
579 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
580
581 #define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */
582 #define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */
583
584 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
585 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
586
587 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
588 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
589
590 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
591 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
592
593 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
594 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
595
596 /** \brief SCB System Control Register Definitions */
597 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
598 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
599
600 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
601 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
602
603 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
604 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
605
606 /** \brief SCB Configuration Control Register Definitions */
607 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
608 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
609
610 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
611 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
612
613 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
614 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
615
616 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
617 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
618
619 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
620 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
621
622 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
623 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
624
625 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
626 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
627
628 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
629 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
630
631 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
632 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
633
634 /** \brief SCB System Handler Control and State Register Definitions */
635 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
636 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
637
638 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
639 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
640
641 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
642 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
643
644 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
645 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
646
647 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
648 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
649
650 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
651 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
652
653 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
654 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
655
656 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
657 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
658
659 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
660 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
661
662 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
663 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
664
665 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
666 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
667
668 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
669 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
670
671 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
672 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
673
674 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
675 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
676
677 /** \brief SCB Configurable Fault Status Register Definitions */
678 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
679 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
680
681 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
682 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
683
684 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
685 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
686
687 /** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */
688 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
689 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
690
691 #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
692 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
693
694 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
695 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
696
697 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
698 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
699
700 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
701 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
702
703 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
704 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
705
706 /** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */
707 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
708 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
709
710 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
711 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
712
713 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
714 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
715
716 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
717 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
718
719 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
720 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
721
722 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
723 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
724
725 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
726 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
727
728 /** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */
729 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
730 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
731
732 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
733 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
734
735 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
736 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
737
738 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
739 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
740
741 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
742 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
743
744 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
745 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
746
747 /** \brief SCB Hard Fault Status Register Definitions */
748 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
749 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
750
751 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
752 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
753
754 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
755 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
756
757 /** \brief SCB Debug Fault Status Register Definitions */
758 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
759 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
760
761 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
762 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
763
764 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
765 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
766
767 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
768 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
769
770 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
771 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
772
773 /** \brief SCB Cache Level ID Register Definitions */
774 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
775 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
776
777 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
778 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
779
780 /** \brief SCB Cache Type Register Definitions */
781 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
782 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
783
784 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
785 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
786
787 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
788 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
789
790 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
791 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
792
793 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
794 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
795
796 /** \brief SCB Cache Size ID Register Definitions */
797 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
798 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
799
800 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
801 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
802
803 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
804 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
805
806 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
807 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
808
809 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
810 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
811
812 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
813 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
814
815 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
816 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
817
818 /** \brief SCB Cache Size Selection Register Definitions */
819 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
820 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
821
822 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
823 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
824
825 /** \brief SCB Software Triggered Interrupt Register Definitions */
826 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
827 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
828
829 /** \brief SCB D-Cache Invalidate by Set-way Register Definitions */
830 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
831 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
832
833 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
834 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
835
836 /** \brief SCB D-Cache Clean by Set-way Register Definitions */
837 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
838 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
839
840 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
841 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
842
843 /** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
844 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
845 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
846
847 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
848 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
849
850 /** \brief SCB Instruction Tightly-Coupled Memory Control Register Definitions */
851 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
852 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
853
854 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
855 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
856
857 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
858 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
859
860 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
861 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
862
863 /** \brief SCB Data Tightly-Coupled Memory Control Register Definitions */
864 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
865 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
866
867 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
868 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
869
870 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
871 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
872
873 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
874 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
875
876 /** \brief SCB AHBP Control Register Definitions */
877 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
878 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
879
880 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
881 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
882
883 /** \brief SCB L1 Cache Control Register Definitions */
884 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
885 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
886
887 #define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */
888 #define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */
889
890 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
891 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
892
893 /** \brief SCB AHBS Control Register Definitions */
894 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
895 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
896
897 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
898 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
899
900 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
901 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
902
903 /** \brief SCB Auxiliary Bus Fault Status Register Definitions */
904 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
905 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
906
907 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
908 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
909
910 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
911 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
912
913 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
914 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
915
916 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
917 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
918
919 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
920 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
921
922 /*@} end of group CMSIS_SCB */
923
924
925 /**
926 \ingroup CMSIS_core_register
927 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
928 \brief Type definitions for the System Control and ID Register not in the SCB
929 @{
930 */
931
932 /**
933 \brief Structure type to access the System Control and ID Register not in the SCB.
934 */
935 typedef struct
936 {
937 uint32_t RESERVED0[1U];
938 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
939 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
940 } SCnSCB_Type;
941
942 /** \brief SCnSCB Interrupt Controller Type Register Definitions */
943 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
944 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
945
946 /** \brief SCnSCB Auxiliary Control Register Definitions */
947 #define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */
948 #define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */
949
950 #define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */
951 #define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */
952
953 #define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */
954 #define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */
955
956 #define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */
957 #define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */
958
959 #define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */
960 #define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */
961
962 #define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */
963 #define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */
964
965 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
966 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
967
968 #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
969 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
970
971 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
972 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
973
974 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
975 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
976
977 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
978 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
979
980 /*@} end of group CMSIS_SCnotSCB */
981
982
983 /**
984 \ingroup CMSIS_core_register
985 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
986 \brief Type definitions for the System Timer Registers.
987 @{
988 */
989
990 /**
991 \brief Structure type to access the System Timer (SysTick).
992 */
993 typedef struct
994 {
995 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
996 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
997 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
998 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
999 } SysTick_Type;
1000
1001 /** \brief SysTick Control / Status Register Definitions */
1002 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
1003 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
1004
1005 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
1006 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
1007
1008 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
1009 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1010
1011 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1012 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1013
1014 /** \brief SysTick Reload Register Definitions */
1015 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
1016 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
1017
1018 /** \brief SysTick Current Register Definitions */
1019 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
1020 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
1021
1022 /** \brief SysTick Calibration Register Definitions */
1023 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
1024 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
1025
1026 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
1027 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
1028
1029 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
1030 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
1031
1032 /*@} end of group CMSIS_SysTick */
1033
1034
1035 /**
1036 \ingroup CMSIS_core_register
1037 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
1038 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
1039 @{
1040 */
1041
1042 /**
1043 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1044 */
1045 typedef struct
1046 {
1047 __OM union
1048 {
1049 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */
1050 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */
1051 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */
1052 } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */
1053 uint32_t RESERVED0[864U];
1054 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */
1055 uint32_t RESERVED1[15U];
1056 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */
1057 uint32_t RESERVED2[15U];
1058 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */
1059 uint32_t RESERVED3[32U];
1060 uint32_t RESERVED4[43U];
1061 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */
1062 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */
1063 } ITM_Type;
1064
1065 /** \brief ITM Trace Privilege Register Definitions */
1066 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
1067 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
1068
1069 /** \brief ITM Trace Control Register Definitions */
1070 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
1071 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
1072
1073 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
1074 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
1075
1076 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
1077 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
1078
1079 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */
1080 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */
1081
1082 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
1083 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
1084
1085 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
1086 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
1087
1088 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
1089 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
1090
1091 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
1092 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
1093
1094 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
1095 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
1096
1097 /** \brief ITM Lock Status Register Definitions */
1098 #define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */
1099 #define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */
1100
1101 #define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */
1102 #define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */
1103
1104 #define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */
1105 #define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */
1106
1107 /*@}*/ /* end of group CMSIS_ITM */
1108
1109
1110 /**
1111 \ingroup CMSIS_core_register
1112 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1113 \brief Type definitions for the Data Watchpoint and Trace (DWT)
1114 @{
1115 */
1116
1117 /**
1118 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1119 */
1120 typedef struct
1121 {
1122 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1123 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
1124 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1125 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
1126 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
1127 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1128 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
1129 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
1130 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1131 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
1132 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1133 uint32_t RESERVED0[1U];
1134 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
1135 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
1136 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1137 uint32_t RESERVED1[1U];
1138 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
1139 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
1140 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1141 uint32_t RESERVED2[1U];
1142 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
1143 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
1144 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1145 uint32_t RESERVED3[981U];
1146 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
1147 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1148 } DWT_Type;
1149
1150 /** \brief DWT Control Register Definitions */
1151 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
1152 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
1153
1154 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
1155 #define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
1156
1157 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
1158 #define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
1159
1160 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
1161 #define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
1162
1163 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
1164 #define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
1165
1166 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
1167 #define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
1168
1169 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
1170 #define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
1171
1172 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
1173 #define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
1174
1175 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
1176 #define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
1177
1178 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
1179 #define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
1180
1181 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
1182 #define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
1183
1184 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
1185 #define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
1186
1187 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
1188 #define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
1189
1190 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
1191 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
1192
1193 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
1194 #define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
1195
1196 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
1197 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
1198
1199 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
1200 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
1201
1202 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
1203 #define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
1204
1205 /** \brief DWT CPI Count Register Definitions */
1206 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
1207 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1208
1209 /** \brief DWT Exception Overhead Count Register Definitions */
1210 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1211 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1212
1213 /** \brief DWT Sleep Count Register Definitions */
1214 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1215 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1216
1217 /** \brief DWT LSU Count Register Definitions */
1218 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1219 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1220
1221 /** \brief DWT Folded-instruction Count Register Definitions */
1222 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1223 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1224
1225 /** \brief DWT Comparator Mask Register Definitions */
1226 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
1227 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
1228
1229 /** \brief DWT Comparator Function Register Definitions */
1230 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1231 #define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1232
1233 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
1234 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
1235
1236 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
1237 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
1238
1239 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1240 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1241
1242 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
1243 #define DWT_FUNCTION_LNK1ENA_Msk (1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
1244
1245 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
1246 #define DWT_FUNCTION_DATAVMATCH_Msk (1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
1247
1248 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
1249 #define DWT_FUNCTION_CYCMATCH_Msk (1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
1250
1251 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
1252 #define DWT_FUNCTION_EMITRANGE_Msk (1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
1253
1254 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
1255 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
1256
1257 /*@}*/ /* end of group CMSIS_DWT */
1258
1259
1260 /**
1261 \ingroup CMSIS_core_register
1262 \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU)
1263 \brief Type definitions for the Trace Port Interface Unit (TPIU)
1264 @{
1265 */
1266
1267 /**
1268 \brief Structure type to access the Trace Port Interface Unit Register (TPIU).
1269 */
1270 typedef struct
1271 {
1272 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1273 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1274 uint32_t RESERVED0[2U];
1275 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1276 uint32_t RESERVED1[55U];
1277 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1278 uint32_t RESERVED2[131U];
1279 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1280 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1281 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1282 uint32_t RESERVED3[759U];
1283 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1284 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1285 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1286 uint32_t RESERVED4[1U];
1287 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1288 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1289 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1290 uint32_t RESERVED5[39U];
1291 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1292 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1293 uint32_t RESERVED7[8U];
1294 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
1295 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
1296 } TPIU_Type;
1297
1298 /** \brief TPIU Asynchronous Clock Prescaler Register Definitions */
1299 #define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */
1300 #define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */
1301
1302 /** \brief TPIU Selected Pin Protocol Register Definitions */
1303 #define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */
1304 #define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */
1305
1306 /** \brief TPIU Formatter and Flush Status Register Definitions */
1307 #define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */
1308 #define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */
1309
1310 #define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */
1311 #define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */
1312
1313 #define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */
1314 #define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */
1315
1316 #define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */
1317 #define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */
1318
1319 /** \brief TPIU Formatter and Flush Control Register Definitions */
1320 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */
1321 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */
1322
1323 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */
1324 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
1325
1326 /** \brief TPIU TRIGGER Register Definitions */
1327 #define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */
1328 #define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */
1329
1330 /** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */
1331 #define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */
1332 #define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */
1333
1334 #define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */
1335 #define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */
1336
1337 #define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */
1338 #define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */
1339
1340 #define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */
1341 #define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0: ETM_bytecount Mask */
1342
1343 #define TPIU_FIFO0_ETM2_Pos 16U /*!< TPIU FIFO0: ETM2 Position */
1344 #define TPIU_FIFO0_ETM2_Msk (0xFFUL << TPIU_FIFO0_ETM2_Pos) /*!< TPIU FIFO0: ETM2 Mask */
1345
1346 #define TPIU_FIFO0_ETM1_Pos 8U /*!< TPIU FIFO0: ETM1 Position */
1347 #define TPIU_FIFO0_ETM1_Msk (0xFFUL << TPIU_FIFO0_ETM1_Pos) /*!< TPIU FIFO0: ETM1 Mask */
1348
1349 #define TPIU_FIFO0_ETM0_Pos 0U /*!< TPIU FIFO0: ETM0 Position */
1350 #define TPIU_FIFO0_ETM0_Msk (0xFFUL /*<< TPIU_FIFO0_ETM0_Pos*/) /*!< TPIU FIFO0: ETM0 Mask */
1351
1352 /** \brief TPIU ITATBCTR2 Register Definitions */
1353 #define TPIU_ITATBCTR2_ATREADY2_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2 Position */
1354 #define TPIU_ITATBCTR2_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2 Mask */
1355
1356 #define TPIU_ITATBCTR2_ATREADY1_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1 Position */
1357 #define TPIU_ITATBCTR2_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1 Mask */
1358
1359 /** \brief TPIU Integration ITM Data Register Definitions (FIFO1) */
1360 #define TPIU_FIFO1_ITM_ATVALID_Pos 29U /*!< TPIU FIFO1: ITM_ATVALID Position */
1361 #define TPIU_FIFO1_ITM_ATVALID_Msk (1UL << TPIU_FIFO1_ITM_ATVALID_Pos) /*!< TPIU FIFO1: ITM_ATVALID Mask */
1362
1363 #define TPIU_FIFO1_ITM_bytecount_Pos 27U /*!< TPIU FIFO1: ITM_bytecount Position */
1364 #define TPIU_FIFO1_ITM_bytecount_Msk (0x3UL << TPIU_FIFO1_ITM_bytecount_Pos) /*!< TPIU FIFO1: ITM_bytecount Mask */
1365
1366 #define TPIU_FIFO1_ETM_ATVALID_Pos 26U /*!< TPIU FIFO1: ETM_ATVALID Position */
1367 #define TPIU_FIFO1_ETM_ATVALID_Msk (1UL << TPIU_FIFO1_ETM_ATVALID_Pos) /*!< TPIU FIFO1: ETM_ATVALID Mask */
1368
1369 #define TPIU_FIFO1_ETM_bytecount_Pos 24U /*!< TPIU FIFO1: ETM_bytecount Position */
1370 #define TPIU_FIFO1_ETM_bytecount_Msk (0x3UL << TPIU_FIFO1_ETM_bytecount_Pos) /*!< TPIU FIFO1: ETM_bytecount Mask */
1371
1372 #define TPIU_FIFO1_ITM2_Pos 16U /*!< TPIU FIFO1: ITM2 Position */
1373 #define TPIU_FIFO1_ITM2_Msk (0xFFUL << TPIU_FIFO1_ITM2_Pos) /*!< TPIU FIFO1: ITM2 Mask */
1374
1375 #define TPIU_FIFO1_ITM1_Pos 8U /*!< TPIU FIFO1: ITM1 Position */
1376 #define TPIU_FIFO1_ITM1_Msk (0xFFUL << TPIU_FIFO1_ITM1_Pos) /*!< TPIU FIFO1: ITM1 Mask */
1377
1378 #define TPIU_FIFO1_ITM0_Pos 0U /*!< TPIU FIFO1: ITM0 Position */
1379 #define TPIU_FIFO1_ITM0_Msk (0xFFUL /*<< TPIU_FIFO1_ITM0_Pos*/) /*!< TPIU FIFO1: ITM0 Mask */
1380
1381 /** \brief TPIU ITATBCTR0 Register Definitions */
1382 #define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */
1383 #define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */
1384
1385 #define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */
1386 #define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */
1387
1388 /** \brief TPIU Integration Mode Control Register Definitions */
1389 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */
1390 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
1391
1392 /** \brief TPIU DEVID Register Definitions */
1393 #define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */
1394 #define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */
1395
1396 #define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */
1397 #define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */
1398
1399 #define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */
1400 #define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */
1401
1402 #define TPIU_DEVID_MinBufSz_Pos 6U /*!< TPIU DEVID: MinBufSz Position */
1403 #define TPIU_DEVID_MinBufSz_Msk (0x7UL << TPIU_DEVID_MinBufSz_Pos) /*!< TPIU DEVID: MinBufSz Mask */
1404
1405 #define TPIU_DEVID_AsynClkIn_Pos 5U /*!< TPIU DEVID: AsynClkIn Position */
1406 #define TPIU_DEVID_AsynClkIn_Msk (1UL << TPIU_DEVID_AsynClkIn_Pos) /*!< TPIU DEVID: AsynClkIn Mask */
1407
1408 #define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */
1409 #define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */
1410
1411 /** \brief TPIU DEVTYPE Register Definitions */
1412 #define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */
1413 #define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */
1414
1415 #define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */
1416 #define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */
1417
1418 /*@}*/ /* end of group CMSIS_TPIU */
1419
1420
1421 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1422 /**
1423 \ingroup CMSIS_core_register
1424 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1425 \brief Type definitions for the Memory Protection Unit (MPU)
1426 @{
1427 */
1428
1429 /**
1430 \brief Structure type to access the Memory Protection Unit (MPU).
1431 */
1432 typedef struct
1433 {
1434 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1435 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1436 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
1437 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1438 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1439 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1440 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1441 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1442 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1443 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1444 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1445 } MPU_Type;
1446
1447 #define MPU_TYPE_RALIASES 4U
1448
1449 /** \brief MPU Type Register Definitions */
1450 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1451 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1452
1453 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1454 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1455
1456 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1457 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1458
1459 /** \brief MPU Control Register Definitions */
1460 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1461 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1462
1463 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1464 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1465
1466 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1467 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1468
1469 /** \brief MPU Region Number Register Definitions */
1470 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1471 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1472
1473 /** \brief MPU Region Base Address Register Definitions */
1474 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1475 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1476
1477 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
1478 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1479
1480 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
1481 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1482
1483 /** \brief MPU Region Attribute and Size Register Definitions */
1484 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
1485 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1486
1487 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
1488 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1489
1490 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
1491 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1492
1493 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
1494 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1495
1496 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
1497 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1498
1499 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
1500 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1501
1502 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
1503 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1504
1505 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
1506 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1507
1508 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
1509 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1510
1511 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
1512 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1513
1514 /*@} end of group CMSIS_MPU */
1515 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1516
1517
1518 /**
1519 \ingroup CMSIS_core_register
1520 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1521 \brief Type definitions for the Floating Point Unit (FPU)
1522 @{
1523 */
1524
1525 /**
1526 \brief Structure type to access the Floating Point Unit (FPU).
1527 */
1528 typedef struct
1529 {
1530 uint32_t RESERVED0[1U];
1531 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1532 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1533 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1534 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
1535 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
1536 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
1537 } FPU_Type;
1538
1539 /** \brief FPU Floating-Point Context Control Register Definitions */
1540 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1541 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1542
1543 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1544 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1545
1546 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1547 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1548
1549 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1550 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1551
1552 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1553 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1554
1555 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1556 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1557
1558 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1559 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1560
1561 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1562 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1563
1564 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1565 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1566
1567 /** \brief FPU Floating-Point Context Address Register Definitions */
1568 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1569 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1570
1571 /** \brief FPU Floating-Point Default Status Control Register Definitions */
1572 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1573 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1574
1575 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1576 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1577
1578 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1579 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1580
1581 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1582 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1583
1584 /** \brief FPU Media and VFP Feature Register 0 Definitions */
1585 #define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */
1586 #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */
1587
1588 #define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */
1589 #define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */
1590
1591 #define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */
1592 #define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */
1593
1594 #define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */
1595 #define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */
1596
1597 #define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */
1598 #define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */
1599
1600 #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */
1601 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */
1602
1603 #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */
1604 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */
1605
1606 #define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */
1607 #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */
1608
1609 /** \brief FPU Media and VFP Feature Register 1 Definitions */
1610 #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */
1611 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */
1612
1613 #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1614 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1615
1616 #define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1617 #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1618
1619 #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1620 #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1621
1622 /** \brief FPU Media and VFP Feature Register 2 Definitions */
1623 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
1624 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
1625
1626 /*@} end of group CMSIS_FPU */
1627
1628
1629 /**
1630 \ingroup CMSIS_core_register
1631 \defgroup CMSIS_DCB Debug Control Block
1632 \brief Type definitions for the Debug Control Block Registers
1633 @{
1634 */
1635
1636 /**
1637 \brief Structure type to access the Debug Control Block Registers (DCB).
1638 */
1639 typedef struct
1640 {
1641 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1642 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1643 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1644 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1645 } DCB_Type;
1646
1647 /** \brief DCB Debug Halting Control and Status Register Definitions */
1648 #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
1649 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
1650
1651 #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
1652 #define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
1653
1654 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
1655 #define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
1656
1657 #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
1658 #define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
1659
1660 #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
1661 #define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
1662
1663 #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
1664 #define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
1665
1666 #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
1667 #define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
1668
1669 #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
1670 #define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
1671
1672 #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
1673 #define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
1674
1675 #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
1676 #define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
1677
1678 #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
1679 #define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
1680
1681 #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
1682 #define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
1683
1684 /** \brief DCB Debug Core Register Selector Register Definitions */
1685 #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
1686 #define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
1687
1688 #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
1689 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
1690
1691 /** \brief DCB Debug Core Register Data Register Definitions */
1692 #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
1693 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
1694
1695 /** \brief DCB Debug Exception and Monitor Control Register Definitions */
1696 #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
1697 #define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
1698
1699 #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
1700 #define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
1701
1702 #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
1703 #define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
1704
1705 #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
1706 #define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
1707
1708 #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
1709 #define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
1710
1711 #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
1712 #define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
1713
1714 #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
1715 #define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
1716
1717 #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
1718 #define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
1719
1720 #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
1721 #define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
1722
1723 #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
1724 #define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
1725
1726 #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
1727 #define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
1728
1729 #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
1730 #define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
1731
1732 #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
1733 #define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
1734
1735 /*@} end of group CMSIS_DCB */
1736
1737
1738 /**
1739 \ingroup CMSIS_core_register
1740 \defgroup CMSIS_core_bitfield Core register bit field macros
1741 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1742 @{
1743 */
1744
1745 /**
1746 \brief Mask and shift a bit field value for use in a register bit range.
1747 \param[in] field Name of the register bit field.
1748 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1749 \return Masked and shifted value.
1750 */
1751 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1752
1753 /**
1754 \brief Mask and shift a register value to extract a bit field value.
1755 \param[in] field Name of the register bit field.
1756 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1757 \return Masked and shifted bit field value.
1758 */
1759 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1760
1761 /*@} end of group CMSIS_core_bitfield */
1762
1763
1764 /**
1765 \ingroup CMSIS_core_register
1766 \defgroup CMSIS_core_base Core Definitions
1767 \brief Definitions for base addresses, unions, and structures.
1768 @{
1769 */
1770
1771 /* Memory mapping of Core Hardware */
1772 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1773 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1774 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1775 #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */
1776 #define DCB_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1777 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1778 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1779 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1780
1781 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1782 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1783 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1784 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1785 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1786 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1787 #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */
1788 #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
1789
1790 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1791 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1792 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1793 #endif
1794
1795 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1796 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1797
1798 /*@} */
1799
1800
1801 /**
1802 \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases
1803 \brief Alias definitions present for backwards compatibility for deprecated symbols.
1804 @{
1805 */
1806
1807 #ifndef CMSIS_DISABLE_DEPRECATED
1808
1809 #define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
1810 #define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk
1811
1812 /* deprecated, CMSIS_5 backward compatibility */
1813 typedef struct
1814 {
1815 __IOM uint32_t DHCSR;
1816 __OM uint32_t DCRSR;
1817 __IOM uint32_t DCRDR;
1818 __IOM uint32_t DEMCR;
1819 } CoreDebug_Type;
1820
1821 /* Debug Halting Control and Status Register Definitions */
1822 #define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos
1823 #define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk
1824
1825 #define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos
1826 #define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk
1827
1828 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos
1829 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk
1830
1831 #define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos
1832 #define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk
1833
1834 #define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos
1835 #define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk
1836
1837 #define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos
1838 #define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk
1839
1840 #define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos
1841 #define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk
1842
1843 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos
1844 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk
1845
1846 #define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos
1847 #define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk
1848
1849 #define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos
1850 #define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk
1851
1852 #define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos
1853 #define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk
1854
1855 #define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos
1856 #define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk
1857
1858 /* Debug Core Register Selector Register Definitions */
1859 #define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos
1860 #define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk
1861
1862 #define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos
1863 #define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk
1864
1865 /* Debug Exception and Monitor Control Register Definitions */
1866 #define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos
1867 #define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk
1868
1869 #define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos
1870 #define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk
1871
1872 #define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos
1873 #define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk
1874
1875 #define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos
1876 #define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk
1877
1878 #define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos
1879 #define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk
1880
1881 #define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos
1882 #define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk
1883
1884 #define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos
1885 #define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk
1886
1887 #define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos
1888 #define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk
1889
1890 #define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos
1891 #define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk
1892
1893 #define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos
1894 #define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk
1895
1896 #define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos
1897 #define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk
1898
1899 #define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos
1900 #define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk
1901
1902 #define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos
1903 #define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk
1904
1905 #define CoreDebug ((CoreDebug_Type *) DCB_BASE)
1906
1907 #endif // CMSIS_DISABLE_DEPRECATED
1908
1909 /*@} */
1910
1911
1912 /*******************************************************************************
1913 * Hardware Abstraction Layer
1914 Core Function Interface contains:
1915 - Core NVIC Functions
1916 - Core SysTick Functions
1917 - Core Debug Functions
1918 - Core Register Access Functions
1919 ******************************************************************************/
1920 /**
1921 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1922 */
1923
1924
1925
1926 /* ########################## NVIC functions #################################### */
1927 /**
1928 \ingroup CMSIS_Core_FunctionInterface
1929 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1930 \brief Functions that manage interrupts and exceptions via the NVIC.
1931 @{
1932 */
1933
1934 #ifdef CMSIS_NVIC_VIRTUAL
1935 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1936 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1937 #endif
1938 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1939 #else
1940 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1941 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1942 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1943 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1944 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1945 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1946 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1947 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1948 #define NVIC_GetActive __NVIC_GetActive
1949 #define NVIC_SetPriority __NVIC_SetPriority
1950 #define NVIC_GetPriority __NVIC_GetPriority
1951 #define NVIC_SystemReset __NVIC_SystemReset
1952 #endif /* CMSIS_NVIC_VIRTUAL */
1953
1954 #ifdef CMSIS_VECTAB_VIRTUAL
1955 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1956 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1957 #endif
1958 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1959 #else
1960 #define NVIC_SetVector __NVIC_SetVector
1961 #define NVIC_GetVector __NVIC_GetVector
1962 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1963
1964 #define NVIC_USER_IRQ_OFFSET 16
1965
1966
1967 /* The following EXC_RETURN values are saved the LR on exception entry */
1968 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
1969 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
1970 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
1971 #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
1972 #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
1973 #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
1974
1975
1976 /**
1977 \brief Set Priority Grouping
1978 \details Sets the priority grouping field using the required unlock sequence.
1979 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1980 Only values from 0..7 are used.
1981 In case of a conflict between priority grouping and available
1982 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1983 \param [in] PriorityGroup Priority grouping field.
1984 */
__NVIC_SetPriorityGrouping(uint32_t PriorityGroup)1985 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1986 {
1987 uint32_t reg_value;
1988 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1989
1990 reg_value = SCB->AIRCR; /* read old register configuration */
1991 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1992 reg_value = (reg_value |
1993 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1994 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
1995 SCB->AIRCR = reg_value;
1996 }
1997
1998
1999 /**
2000 \brief Get Priority Grouping
2001 \details Reads the priority grouping field from the NVIC Interrupt Controller.
2002 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2003 */
__NVIC_GetPriorityGrouping(void)2004 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2005 {
2006 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2007 }
2008
2009
2010 /**
2011 \brief Enable Interrupt
2012 \details Enables a device specific interrupt in the NVIC interrupt controller.
2013 \param [in] IRQn Device specific interrupt number.
2014 \note IRQn must not be negative.
2015 */
__NVIC_EnableIRQ(IRQn_Type IRQn)2016 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2017 {
2018 if ((int32_t)(IRQn) >= 0)
2019 {
2020 __COMPILER_BARRIER();
2021 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2022 __COMPILER_BARRIER();
2023 }
2024 }
2025
2026
2027 /**
2028 \brief Get Interrupt Enable status
2029 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
2030 \param [in] IRQn Device specific interrupt number.
2031 \return 0 Interrupt is not enabled.
2032 \return 1 Interrupt is enabled.
2033 \note IRQn must not be negative.
2034 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)2035 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2036 {
2037 if ((int32_t)(IRQn) >= 0)
2038 {
2039 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2040 }
2041 else
2042 {
2043 return(0U);
2044 }
2045 }
2046
2047
2048 /**
2049 \brief Disable Interrupt
2050 \details Disables a device specific interrupt in the NVIC interrupt controller.
2051 \param [in] IRQn Device specific interrupt number.
2052 \note IRQn must not be negative.
2053 */
__NVIC_DisableIRQ(IRQn_Type IRQn)2054 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2055 {
2056 if ((int32_t)(IRQn) >= 0)
2057 {
2058 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2059 __DSB();
2060 __ISB();
2061 }
2062 }
2063
2064
2065 /**
2066 \brief Get Pending Interrupt
2067 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
2068 \param [in] IRQn Device specific interrupt number.
2069 \return 0 Interrupt status is not pending.
2070 \return 1 Interrupt status is pending.
2071 \note IRQn must not be negative.
2072 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)2073 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2074 {
2075 if ((int32_t)(IRQn) >= 0)
2076 {
2077 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2078 }
2079 else
2080 {
2081 return(0U);
2082 }
2083 }
2084
2085
2086 /**
2087 \brief Set Pending Interrupt
2088 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
2089 \param [in] IRQn Device specific interrupt number.
2090 \note IRQn must not be negative.
2091 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)2092 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2093 {
2094 if ((int32_t)(IRQn) >= 0)
2095 {
2096 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2097 }
2098 }
2099
2100
2101 /**
2102 \brief Clear Pending Interrupt
2103 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
2104 \param [in] IRQn Device specific interrupt number.
2105 \note IRQn must not be negative.
2106 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)2107 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2108 {
2109 if ((int32_t)(IRQn) >= 0)
2110 {
2111 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2112 }
2113 }
2114
2115
2116 /**
2117 \brief Get Active Interrupt
2118 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
2119 \param [in] IRQn Device specific interrupt number.
2120 \return 0 Interrupt status is not active.
2121 \return 1 Interrupt status is active.
2122 \note IRQn must not be negative.
2123 */
__NVIC_GetActive(IRQn_Type IRQn)2124 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2125 {
2126 if ((int32_t)(IRQn) >= 0)
2127 {
2128 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2129 }
2130 else
2131 {
2132 return(0U);
2133 }
2134 }
2135
2136
2137 /**
2138 \brief Set Interrupt Priority
2139 \details Sets the priority of a device specific interrupt or a processor exception.
2140 The interrupt number can be positive to specify a device specific interrupt,
2141 or negative to specify a processor exception.
2142 \param [in] IRQn Interrupt number.
2143 \param [in] priority Priority to set.
2144 \note The priority cannot be set for every processor exception.
2145 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)2146 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2147 {
2148 if ((int32_t)(IRQn) >= 0)
2149 {
2150 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2151 }
2152 else
2153 {
2154 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2155 }
2156 }
2157
2158
2159 /**
2160 \brief Get Interrupt Priority
2161 \details Reads the priority of a device specific interrupt or a processor exception.
2162 The interrupt number can be positive to specify a device specific interrupt,
2163 or negative to specify a processor exception.
2164 \param [in] IRQn Interrupt number.
2165 \return Interrupt Priority.
2166 Value is aligned automatically to the implemented priority bits of the microcontroller.
2167 */
__NVIC_GetPriority(IRQn_Type IRQn)2168 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2169 {
2170
2171 if ((int32_t)(IRQn) >= 0)
2172 {
2173 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2174 }
2175 else
2176 {
2177 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2178 }
2179 }
2180
2181
2182 /**
2183 \brief Encode Priority
2184 \details Encodes the priority for an interrupt with the given priority group,
2185 preemptive priority value, and subpriority value.
2186 In case of a conflict between priority grouping and available
2187 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2188 \param [in] PriorityGroup Used priority group.
2189 \param [in] PreemptPriority Preemptive priority value (starting from 0).
2190 \param [in] SubPriority Subpriority value (starting from 0).
2191 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
2192 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)2193 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2194 {
2195 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2196 uint32_t PreemptPriorityBits;
2197 uint32_t SubPriorityBits;
2198
2199 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2200 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2201
2202 return (
2203 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2204 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2205 );
2206 }
2207
2208
2209 /**
2210 \brief Decode Priority
2211 \details Decodes an interrupt priority value with a given priority group to
2212 preemptive priority value and subpriority value.
2213 In case of a conflict between priority grouping and available
2214 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
2215 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
2216 \param [in] PriorityGroup Used priority group.
2217 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
2218 \param [out] pSubPriority Subpriority value (starting from 0).
2219 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)2220 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2221 {
2222 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2223 uint32_t PreemptPriorityBits;
2224 uint32_t SubPriorityBits;
2225
2226 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2227 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2228
2229 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2230 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2231 }
2232
2233
2234 /**
2235 \brief Set Interrupt Vector
2236 \details Sets an interrupt vector in SRAM based interrupt vector table.
2237 The interrupt number can be positive to specify a device specific interrupt,
2238 or negative to specify a processor exception.
2239 VTOR must been relocated to SRAM before.
2240 \param [in] IRQn Interrupt number
2241 \param [in] vector Address of interrupt handler function
2242 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)2243 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2244 {
2245 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
2246 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2247 __DSB();
2248 }
2249
2250
2251 /**
2252 \brief Get Interrupt Vector
2253 \details Reads an interrupt vector from interrupt vector table.
2254 The interrupt number can be positive to specify a device specific interrupt,
2255 or negative to specify a processor exception.
2256 \param [in] IRQn Interrupt number.
2257 \return Address of interrupt handler function
2258 */
__NVIC_GetVector(IRQn_Type IRQn)2259 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2260 {
2261 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
2262 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2263 }
2264
2265
2266 /**
2267 \brief System Reset
2268 \details Initiates a system reset request to reset the MCU.
2269 */
__NVIC_SystemReset(void)2270 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2271 {
2272 __DSB(); /* Ensure all outstanding memory accesses included
2273 buffered write are completed before reset */
2274 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2275 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2276 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2277 __DSB(); /* Ensure completion of memory access */
2278
2279 for(;;) /* wait until reset */
2280 {
2281 __NOP();
2282 }
2283 }
2284
2285 /*@} end of CMSIS_Core_NVICFunctions */
2286
2287
2288 /* ########################## MPU functions #################################### */
2289
2290 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2291
2292 #include "m-profile/armv7m_mpu.h"
2293
2294 #endif
2295
2296
2297 /* ########################## FPU functions #################################### */
2298 /**
2299 \ingroup CMSIS_Core_FunctionInterface
2300 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2301 \brief Function that provides FPU type.
2302 @{
2303 */
2304
2305 /**
2306 \brief get FPU type
2307 \details returns the FPU type
2308 \returns
2309 - \b 0: No FPU
2310 - \b 1: Single precision FPU
2311 - \b 2: Double + Single precision FPU
2312 */
SCB_GetFPUType(void)2313 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2314 {
2315 uint32_t mvfr0;
2316
2317 mvfr0 = FPU->MVFR0;
2318 if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
2319 {
2320 return 2U; /* Double + Single precision FPU */
2321 }
2322 else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
2323 {
2324 return 1U; /* Single precision FPU */
2325 }
2326 else
2327 {
2328 return 0U; /* No FPU */
2329 }
2330 }
2331
2332 /*@} end of CMSIS_Core_FpuFunctions */
2333
2334
2335 /* ########################## Cache functions #################################### */
2336
2337 #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
2338 (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
2339 #include "m-profile/armv7m_cachel1.h"
2340 #endif
2341
2342
2343 /* ################################## SysTick function ############################################ */
2344 /**
2345 \ingroup CMSIS_Core_FunctionInterface
2346 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2347 \brief Functions that configure the System.
2348 @{
2349 */
2350
2351 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2352
2353 /**
2354 \brief System Tick Configuration
2355 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2356 Counter is in free running mode to generate periodic interrupts.
2357 \param [in] ticks Number of ticks between two interrupts.
2358 \return 0 Function succeeded.
2359 \return 1 Function failed.
2360 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2361 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2362 must contain a vendor-specific implementation of this function.
2363 */
SysTick_Config(uint32_t ticks)2364 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2365 {
2366 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2367 {
2368 return (1UL); /* Reload value impossible */
2369 }
2370
2371 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2372 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2373 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2374 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2375 SysTick_CTRL_TICKINT_Msk |
2376 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2377 return (0UL); /* Function successful */
2378 }
2379
2380 #endif
2381
2382 /*@} end of CMSIS_Core_SysTickFunctions */
2383
2384
2385
2386 /* ##################################### Debug In/Output function ########################################### */
2387 /**
2388 \ingroup CMSIS_Core_FunctionInterface
2389 \defgroup CMSIS_core_DebugFunctions ITM Functions
2390 \brief Functions that access the ITM debug interface.
2391 @{
2392 */
2393
2394 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
2395 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2396
2397
2398 /**
2399 \brief ITM Send Character
2400 \details Transmits a character via the ITM channel 0, and
2401 \li Just returns when no debugger is connected that has booked the output.
2402 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2403 \param [in] ch Character to transmit.
2404 \returns Character to transmit.
2405 */
ITM_SendChar(uint32_t ch)2406 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2407 {
2408 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2409 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2410 {
2411 while (ITM->PORT[0U].u32 == 0UL)
2412 {
2413 __NOP();
2414 }
2415 ITM->PORT[0U].u8 = (uint8_t)ch;
2416 }
2417 return (ch);
2418 }
2419
2420
2421 /**
2422 \brief ITM Receive Character
2423 \details Inputs a character via the external variable \ref ITM_RxBuffer.
2424 \return Received character.
2425 \return -1 No character pending.
2426 */
ITM_ReceiveChar(void)2427 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2428 {
2429 int32_t ch = -1; /* no character available */
2430
2431 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2432 {
2433 ch = ITM_RxBuffer;
2434 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2435 }
2436
2437 return (ch);
2438 }
2439
2440
2441 /**
2442 \brief ITM Check Character
2443 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2444 \return 0 No character available.
2445 \return 1 Character available.
2446 */
ITM_CheckChar(void)2447 __STATIC_INLINE int32_t ITM_CheckChar (void)
2448 {
2449
2450 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2451 {
2452 return (0); /* no character available */
2453 }
2454 else
2455 {
2456 return (1); /* character available */
2457 }
2458 }
2459
2460 /*@} end of CMSIS_core_DebugFunctions */
2461
2462
2463
2464
2465 #ifdef __cplusplus
2466 }
2467 #endif
2468
2469 #endif /* __CORE_CM7_H_DEPENDANT */
2470
2471 #endif /* __CMSIS_GENERIC */
2472
