1 /*
2 * Copyright (c) 2009-2024 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * CMSIS Cortex-M1 Core Peripheral Access Layer Header File
21 */
22
23 #if defined ( __ICCARM__ )
24 #pragma system_include /* treat file as system include file for MISRA check */
25 #elif defined (__clang__)
26 #pragma clang system_header /* treat file as system include file */
27 #elif defined ( __GNUC__ )
28 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
29 #endif
30
31 #ifndef __CORE_CM1_H_GENERIC
32 #define __CORE_CM1_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup Cortex_M1
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS CM1 definitions */
66
67 #define __CORTEX_M (1U) /*!< Cortex-M Core */
68
69 /** __FPU_USED indicates whether an FPU is used or not.
70 This core does not support an FPU at all
71 */
72 #define __FPU_USED 0U
73
74 #if defined ( __CC_ARM )
75 #if defined (__TARGET_FPU_VFP)
76 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
77 #endif
78
79 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
80 #if defined (__ARM_FP)
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82 #endif
83
84 #elif defined (__ti__)
85 #if defined (__ARM_FP)
86 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
87 #endif
88
89 #elif defined ( __GNUC__ )
90 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
91 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
92 #endif
93
94 #elif defined ( __ICCARM__ )
95 #if defined (__ARMVFP__)
96 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
97 #endif
98
99 #elif defined ( __TI_ARM__ )
100 #if defined (__TI_VFP_SUPPORT__)
101 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
102 #endif
103
104 #elif defined ( __TASKING__ )
105 #if defined (__FPU_VFP__)
106 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
107 #endif
108
109 #elif defined ( __CSMC__ )
110 #if ( __CSMC__ & 0x400U)
111 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
112 #endif
113
114 #endif
115
116 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
117
118
119 #ifdef __cplusplus
120 }
121 #endif
122
123 #endif /* __CORE_CM1_H_GENERIC */
124
125 #ifndef __CMSIS_GENERIC
126
127 #ifndef __CORE_CM1_H_DEPENDANT
128 #define __CORE_CM1_H_DEPENDANT
129
130 #ifdef __cplusplus
131 extern "C" {
132 #endif
133
134 /* check device defines and use defaults */
135 #if defined __CHECK_DEVICE_DEFINES
136 #ifndef __CM1_REV
137 #define __CM1_REV 0x0100U
138 #warning "__CM1_REV not defined in device header file; using default!"
139 #endif
140
141 #ifndef __NVIC_PRIO_BITS
142 #define __NVIC_PRIO_BITS 2U
143 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
144 #endif
145
146 #ifndef __Vendor_SysTickConfig
147 #define __Vendor_SysTickConfig 0U
148 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
149 #endif
150 #endif
151
152 /* IO definitions (access restrictions to peripheral registers) */
153 /**
154 \defgroup CMSIS_glob_defs CMSIS Global Defines
155
156 <strong>IO Type Qualifiers</strong> are used
157 \li to specify the access to peripheral variables.
158 \li for automatic generation of peripheral register debug information.
159 */
160 #ifdef __cplusplus
161 #define __I volatile /*!< Defines 'read only' permissions */
162 #else
163 #define __I volatile const /*!< Defines 'read only' permissions */
164 #endif
165 #define __O volatile /*!< Defines 'write only' permissions */
166 #define __IO volatile /*!< Defines 'read / write' permissions */
167
168 /* following defines should be used for structure members */
169 #define __IM volatile const /*! Defines 'read only' structure member permissions */
170 #define __OM volatile /*! Defines 'write only' structure member permissions */
171 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
172
173 /*@} end of group Cortex_M1 */
174
175
176
177 /*******************************************************************************
178 * Register Abstraction
179 Core Register contain:
180 - Core Register
181 - Core NVIC Register
182 - Core SCB Register
183 - Core SysTick Register
184 ******************************************************************************/
185 /**
186 \defgroup CMSIS_core_register Defines and Type Definitions
187 \brief Type definitions and defines for Cortex-M processor based devices.
188 */
189
190 /**
191 \ingroup CMSIS_core_register
192 \defgroup CMSIS_CORE Status and Control Registers
193 \brief Core Register type definitions.
194 @{
195 */
196
197 /**
198 \brief Union type to access the Application Program Status Register (APSR).
199 */
200 typedef union
201 {
202 struct
203 {
204 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
205 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
206 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
207 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
208 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
209 } b; /*!< Structure used for bit access */
210 uint32_t w; /*!< Type used for word access */
211 } APSR_Type;
212
213 /** \brief APSR Register Definitions */
214 #define APSR_N_Pos 31U /*!< APSR: N Position */
215 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
216
217 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
218 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
219
220 #define APSR_C_Pos 29U /*!< APSR: C Position */
221 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
222
223 #define APSR_V_Pos 28U /*!< APSR: V Position */
224 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
225
226
227 /**
228 \brief Union type to access the Interrupt Program Status Register (IPSR).
229 */
230 typedef union
231 {
232 struct
233 {
234 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
235 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
236 } b; /*!< Structure used for bit access */
237 uint32_t w; /*!< Type used for word access */
238 } IPSR_Type;
239
240 /** \brief IPSR Register Definitions */
241 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
242 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
243
244
245 /**
246 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
247 */
248 typedef union
249 {
250 struct
251 {
252 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
253 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
255 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
256 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
257 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
258 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
259 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
260 } b; /*!< Structure used for bit access */
261 uint32_t w; /*!< Type used for word access */
262 } xPSR_Type;
263
264 /** \brief xPSR Register Definitions */
265 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
266 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
267
268 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
269 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
270
271 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
272 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
273
274 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
275 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
276
277 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
278 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
279
280 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
281 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
282
283
284 /**
285 \brief Union type to access the Control Registers (CONTROL).
286 */
287 typedef union
288 {
289 struct
290 {
291 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
292 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
293 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
294 } b; /*!< Structure used for bit access */
295 uint32_t w; /*!< Type used for word access */
296 } CONTROL_Type;
297
298 /** \brief CONTROL Register Definitions */
299 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
300 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
301
302 /*@} end of group CMSIS_CORE */
303
304
305 /**
306 \ingroup CMSIS_core_register
307 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
308 \brief Type definitions for the NVIC Registers
309 @{
310 */
311
312 /**
313 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
314 */
315 typedef struct
316 {
317 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
318 uint32_t RESERVED0[31U];
319 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
320 uint32_t RESERVED1[31U];
321 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
322 uint32_t RESERVED2[31U];
323 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
324 uint32_t RESERVED3[31U];
325 uint32_t RESERVED4[64U];
326 __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
327 } NVIC_Type;
328
329 /*@} end of group CMSIS_NVIC */
330
331
332 /**
333 \ingroup CMSIS_core_register
334 \defgroup CMSIS_SCB System Control Block (SCB)
335 \brief Type definitions for the System Control Block Registers
336 @{
337 */
338
339 /**
340 \brief Structure type to access the System Control Block (SCB).
341 */
342 typedef struct
343 {
344 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
345 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
346 uint32_t RESERVED0;
347 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
348 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
349 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
350 uint32_t RESERVED1;
351 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
352 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
353 } SCB_Type;
354
355 /** \brief SCB CPUID Register Definitions */
356 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
357 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
358
359 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
360 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
361
362 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
363 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
364
365 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
366 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
367
368 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
369 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
370
371 /** \brief SCB Interrupt Control State Register Definitions */
372 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
373 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
374
375 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
376 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
377
378 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
379 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
380
381 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
382 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
383
384 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
385 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
386
387 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
388 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
389
390 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
391 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
392
393 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
394 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
395
396 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
397 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
398
399 /** \brief SCB Application Interrupt and Reset Control Register Definitions */
400 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
401 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
402
403 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
404 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
405
406 #define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */
407 #define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */
408
409 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
410 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
411
412 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
413 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
414
415 /** \brief SCB System Control Register Definitions */
416 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
417 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
418
419 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
420 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
421
422 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
423 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
424
425 /** \brief SCB Configuration Control Register Definitions */
426 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
427 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
428
429 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
430 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
431
432 /** \brief SCB System Handler Control and State Register Definitions */
433 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
434 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
435
436 /*@} end of group CMSIS_SCB */
437
438
439 /**
440 \ingroup CMSIS_core_register
441 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
442 \brief Type definitions for the System Control and ID Register not in the SCB
443 @{
444 */
445
446 /**
447 \brief Structure type to access the System Control and ID Register not in the SCB.
448 */
449 typedef struct
450 {
451 uint32_t RESERVED0[2U];
452 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
453 } SCnSCB_Type;
454
455 /** \brief SCnSCB Auxiliary Control Register Definitions */
456 #define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
457 #define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
458
459 #define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
460 #define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
461
462 /*@} end of group CMSIS_SCnotSCB */
463
464
465 /**
466 \ingroup CMSIS_core_register
467 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
468 \brief Type definitions for the System Timer Registers.
469 @{
470 */
471
472 /**
473 \brief Structure type to access the System Timer (SysTick).
474 */
475 typedef struct
476 {
477 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
478 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
479 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
480 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
481 } SysTick_Type;
482
483 /** \brief SysTick Control / Status Register Definitions */
484 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
485 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
486
487 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
488 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
489
490 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
491 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
492
493 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
494 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
495
496 /** \brief SysTick Reload Register Definitions */
497 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
498 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
499
500 /** \brief SysTick Current Register Definitions */
501 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
502 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
503
504 /** \brief SysTick Calibration Register Definitions */
505 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
506 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
507
508 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
509 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
510
511 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
512 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
513
514 /*@} end of group CMSIS_SysTick */
515
516
517 /**
518 \ingroup CMSIS_core_register
519 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
520 \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
521 Therefore they are not covered by the Cortex-M1 header file.
522 @{
523 */
524 /*@} end of group CMSIS_CoreDebug */
525
526
527 /**
528 \ingroup CMSIS_core_register
529 \defgroup CMSIS_core_bitfield Core register bit field macros
530 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
531 @{
532 */
533
534 /**
535 \brief Mask and shift a bit field value for use in a register bit range.
536 \param[in] field Name of the register bit field.
537 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
538 \return Masked and shifted value.
539 */
540 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
541
542 /**
543 \brief Mask and shift a register value to extract a bit field value.
544 \param[in] field Name of the register bit field.
545 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
546 \return Masked and shifted bit field value.
547 */
548 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
549
550 /*@} end of group CMSIS_core_bitfield */
551
552
553 /**
554 \ingroup CMSIS_core_register
555 \defgroup CMSIS_core_base Core Definitions
556 \brief Definitions for base addresses, unions, and structures.
557 @{
558 */
559
560 /* Memory mapping of Core Hardware */
561 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
562 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
563 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
564 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
565
566 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
567 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
568 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
569 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
570
571
572 /*@} */
573
574
575 /**
576 \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases
577 \brief Alias definitions present for backwards compatibility for deprecated symbols.
578 @{
579 */
580
581 #ifndef CMSIS_DISABLE_DEPRECATED
582
583 #define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
584 #define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk
585
586 #endif // CMSIS_DISABLE_DEPRECATED
587
588 /*@} */
589
590
591 /*******************************************************************************
592 * Hardware Abstraction Layer
593 Core Function Interface contains:
594 - Core NVIC Functions
595 - Core SysTick Functions
596 - Core Register Access Functions
597 ******************************************************************************/
598 /**
599 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
600 */
601
602
603
604 /* ########################## NVIC functions #################################### */
605 /**
606 \ingroup CMSIS_Core_FunctionInterface
607 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
608 \brief Functions that manage interrupts and exceptions via the NVIC.
609 @{
610 */
611
612 #ifdef CMSIS_NVIC_VIRTUAL
613 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
614 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
615 #endif
616 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
617 #else
618 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
619 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
620 #define NVIC_EnableIRQ __NVIC_EnableIRQ
621 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
622 #define NVIC_DisableIRQ __NVIC_DisableIRQ
623 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
624 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
625 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
626 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
627 #define NVIC_SetPriority __NVIC_SetPriority
628 #define NVIC_GetPriority __NVIC_GetPriority
629 #define NVIC_SystemReset __NVIC_SystemReset
630 #endif /* CMSIS_NVIC_VIRTUAL */
631
632 #ifdef CMSIS_VECTAB_VIRTUAL
633 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
634 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
635 #endif
636 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
637 #else
638 #define NVIC_SetVector __NVIC_SetVector
639 #define NVIC_GetVector __NVIC_GetVector
640 #endif /* (CMSIS_VECTAB_VIRTUAL) */
641
642 #define NVIC_USER_IRQ_OFFSET 16
643
644
645 /* The following EXC_RETURN values are saved the LR on exception entry */
646 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
647 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
648 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
649
650
651 /* Interrupt Priorities are WORD accessible only under Armv6-M */
652 /* The following MACROS handle generation of the register offset and byte masks */
653 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
654 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
655 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
656
657 #define __NVIC_SetPriorityGrouping(X) (void)(X)
658 #define __NVIC_GetPriorityGrouping() (0U)
659
660 /**
661 \brief Enable Interrupt
662 \details Enables a device specific interrupt in the NVIC interrupt controller.
663 \param [in] IRQn Device specific interrupt number.
664 \note IRQn must not be negative.
665 */
__NVIC_EnableIRQ(IRQn_Type IRQn)666 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
667 {
668 if ((int32_t)(IRQn) >= 0)
669 {
670 __COMPILER_BARRIER();
671 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
672 __COMPILER_BARRIER();
673 }
674 }
675
676
677 /**
678 \brief Get Interrupt Enable status
679 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
680 \param [in] IRQn Device specific interrupt number.
681 \return 0 Interrupt is not enabled.
682 \return 1 Interrupt is enabled.
683 \note IRQn must not be negative.
684 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)685 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
686 {
687 if ((int32_t)(IRQn) >= 0)
688 {
689 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
690 }
691 else
692 {
693 return(0U);
694 }
695 }
696
697
698 /**
699 \brief Disable Interrupt
700 \details Disables a device specific interrupt in the NVIC interrupt controller.
701 \param [in] IRQn Device specific interrupt number.
702 \note IRQn must not be negative.
703 */
__NVIC_DisableIRQ(IRQn_Type IRQn)704 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
705 {
706 if ((int32_t)(IRQn) >= 0)
707 {
708 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
709 __DSB();
710 __ISB();
711 }
712 }
713
714
715 /**
716 \brief Get Pending Interrupt
717 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
718 \param [in] IRQn Device specific interrupt number.
719 \return 0 Interrupt status is not pending.
720 \return 1 Interrupt status is pending.
721 \note IRQn must not be negative.
722 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)723 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
724 {
725 if ((int32_t)(IRQn) >= 0)
726 {
727 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
728 }
729 else
730 {
731 return(0U);
732 }
733 }
734
735
736 /**
737 \brief Set Pending Interrupt
738 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
739 \param [in] IRQn Device specific interrupt number.
740 \note IRQn must not be negative.
741 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)742 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
743 {
744 if ((int32_t)(IRQn) >= 0)
745 {
746 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
747 }
748 }
749
750
751 /**
752 \brief Clear Pending Interrupt
753 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
754 \param [in] IRQn Device specific interrupt number.
755 \note IRQn must not be negative.
756 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)757 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
758 {
759 if ((int32_t)(IRQn) >= 0)
760 {
761 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
762 }
763 }
764
765
766 /**
767 \brief Set Interrupt Priority
768 \details Sets the priority of a device specific interrupt or a processor exception.
769 The interrupt number can be positive to specify a device specific interrupt,
770 or negative to specify a processor exception.
771 \param [in] IRQn Interrupt number.
772 \param [in] priority Priority to set.
773 \note The priority cannot be set for every processor exception.
774 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)775 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
776 {
777 if ((int32_t)(IRQn) >= 0)
778 {
779 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
780 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
781 }
782 else
783 {
784 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
785 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
786 }
787 }
788
789
790 /**
791 \brief Get Interrupt Priority
792 \details Reads the priority of a device specific interrupt or a processor exception.
793 The interrupt number can be positive to specify a device specific interrupt,
794 or negative to specify a processor exception.
795 \param [in] IRQn Interrupt number.
796 \return Interrupt Priority.
797 Value is aligned automatically to the implemented priority bits of the microcontroller.
798 */
__NVIC_GetPriority(IRQn_Type IRQn)799 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
800 {
801
802 if ((int32_t)(IRQn) >= 0)
803 {
804 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
805 }
806 else
807 {
808 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
809 }
810 }
811
812
813 /**
814 \brief Encode Priority
815 \details Encodes the priority for an interrupt with the given priority group,
816 preemptive priority value, and subpriority value.
817 In case of a conflict between priority grouping and available
818 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
819 \param [in] PriorityGroup Used priority group.
820 \param [in] PreemptPriority Preemptive priority value (starting from 0).
821 \param [in] SubPriority Subpriority value (starting from 0).
822 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
823 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)824 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
825 {
826 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
827 uint32_t PreemptPriorityBits;
828 uint32_t SubPriorityBits;
829
830 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
831 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
832
833 return (
834 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
835 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
836 );
837 }
838
839
840 /**
841 \brief Decode Priority
842 \details Decodes an interrupt priority value with a given priority group to
843 preemptive priority value and subpriority value.
844 In case of a conflict between priority grouping and available
845 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
846 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
847 \param [in] PriorityGroup Used priority group.
848 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
849 \param [out] pSubPriority Subpriority value (starting from 0).
850 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)851 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
852 {
853 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
854 uint32_t PreemptPriorityBits;
855 uint32_t SubPriorityBits;
856
857 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
858 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
859
860 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
861 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
862 }
863
864
865 /**
866 \brief Set Interrupt Vector
867 \details Sets an interrupt vector in SRAM based interrupt vector table.
868 The interrupt number can be positive to specify a device specific interrupt,
869 or negative to specify a processor exception.
870 Address 0 must be mapped to SRAM.
871 \param [in] IRQn Interrupt number
872 \param [in] vector Address of interrupt handler function
873 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)874 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
875 {
876 uint32_t *vectors = (uint32_t *)0x0U;
877 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
878 /* ARM Application Note 321 states that the M1 does not require the architectural barrier */
879 }
880
881
882 /**
883 \brief Get Interrupt Vector
884 \details Reads an interrupt vector from interrupt vector table.
885 The interrupt number can be positive to specify a device specific interrupt,
886 or negative to specify a processor exception.
887 \param [in] IRQn Interrupt number.
888 \return Address of interrupt handler function
889 */
__NVIC_GetVector(IRQn_Type IRQn)890 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
891 {
892 uint32_t *vectors = (uint32_t *)0x0U;
893 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
894 }
895
896
897 /**
898 \brief System Reset
899 \details Initiates a system reset request to reset the MCU.
900 */
__NVIC_SystemReset(void)901 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
902 {
903 __DSB(); /* Ensure all outstanding memory accesses included
904 buffered write are completed before reset */
905 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
906 SCB_AIRCR_SYSRESETREQ_Msk);
907 __DSB(); /* Ensure completion of memory access */
908
909 for(;;) /* wait until reset */
910 {
911 __NOP();
912 }
913 }
914
915 /*@} end of CMSIS_Core_NVICFunctions */
916
917
918 /* ########################## FPU functions #################################### */
919 /**
920 \ingroup CMSIS_Core_FunctionInterface
921 \defgroup CMSIS_Core_FpuFunctions FPU Functions
922 \brief Function that provides FPU type.
923 @{
924 */
925
926 /**
927 \brief get FPU type
928 \details returns the FPU type
929 \returns
930 - \b 0: No FPU
931 - \b 1: Single precision FPU
932 - \b 2: Double + Single precision FPU
933 */
SCB_GetFPUType(void)934 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
935 {
936 return 0U; /* No FPU */
937 }
938
939 /*@} end of CMSIS_Core_FpuFunctions */
940
941
942 /* ################################## SysTick function ############################################ */
943 /**
944 \ingroup CMSIS_Core_FunctionInterface
945 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
946 \brief Functions that configure the System.
947 @{
948 */
949
950 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
951
952 /**
953 \brief System Tick Configuration
954 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
955 Counter is in free running mode to generate periodic interrupts.
956 \param [in] ticks Number of ticks between two interrupts.
957 \return 0 Function succeeded.
958 \return 1 Function failed.
959 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
960 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
961 must contain a vendor-specific implementation of this function.
962 */
SysTick_Config(uint32_t ticks)963 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
964 {
965 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
966 {
967 return (1UL); /* Reload value impossible */
968 }
969
970 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
971 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
972 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
973 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
974 SysTick_CTRL_TICKINT_Msk |
975 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
976 return (0UL); /* Function successful */
977 }
978
979 #endif
980
981 /*@} end of CMSIS_Core_SysTickFunctions */
982
983
984
985
986 #ifdef __cplusplus
987 }
988 #endif
989
990 #endif /* __CORE_CM1_H_DEPENDANT */
991
992 #endif /* __CMSIS_GENERIC */
993
