1 /*
2 * Copyright (c) 2018-2024 Arm Limited. Copyright (c) 2024 Arm Technology (China) Co., Ltd. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * CMSIS Cortex-M52 Core Peripheral Access Layer Header File
21 */
22
23 #if defined ( __ICCARM__ )
24 #pragma system_include /* treat file as system include file for MISRA check */
25 #elif defined (__clang__)
26 #pragma clang system_header /* treat file as system include file */
27 #elif defined ( __GNUC__ )
28 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
29 #endif
30
31 #ifndef __CORE_CM52_H_GENERIC
32 #define __CORE_CM52_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup Cortex_M52
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS CM52 definitions */
66
67 #define __CORTEX_M (52U) /*!< Cortex-M Core */
68
69 #if defined ( __CC_ARM )
70 #error Legacy Arm Compiler does not support Armv8.1-M target architecture.
71 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
72 #if defined (__ARM_FP)
73 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
74 #define __FPU_USED 1U
75 #else
76 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
77 #define __FPU_USED 0U
78 #endif
79 #else
80 #define __FPU_USED 0U
81 #endif
82
83 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
84 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
85 #define __DSP_USED 1U
86 #else
87 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
88 #define __DSP_USED 0U
89 #endif
90 #else
91 #define __DSP_USED 0U
92 #endif
93
94 #elif defined (__ti__)
95 #if defined (__ARM_FP)
96 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
97 #define __FPU_USED 1U
98 #else
99 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
100 #define __FPU_USED 0U
101 #endif
102 #else
103 #define __FPU_USED 0U
104 #endif
105
106 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
107 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
108 #define __DSP_USED 1U
109 #else
110 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
111 #define __DSP_USED 0U
112 #endif
113 #else
114 #define __DSP_USED 0U
115 #endif
116
117 #elif defined ( __GNUC__ )
118 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
119 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
120 #define __FPU_USED 1U
121 #else
122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
123 #define __FPU_USED 0U
124 #endif
125 #else
126 #define __FPU_USED 0U
127 #endif
128
129 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
130 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
131 #define __DSP_USED 1U
132 #else
133 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
134 #define __DSP_USED 0U
135 #endif
136 #else
137 #define __DSP_USED 0U
138 #endif
139
140 #elif defined ( __ICCARM__ )
141 #if defined (__ARMVFP__)
142 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
143 #define __FPU_USED 1U
144 #else
145 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
146 #define __FPU_USED 0U
147 #endif
148 #else
149 #define __FPU_USED 0U
150 #endif
151
152 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
153 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
154 #define __DSP_USED 1U
155 #else
156 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
157 #define __DSP_USED 0U
158 #endif
159 #else
160 #define __DSP_USED 0U
161 #endif
162
163 #elif defined ( __TI_ARM__ )
164 #if defined (__TI_VFP_SUPPORT__)
165 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
166 #define __FPU_USED 1U
167 #else
168 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
169 #define __FPU_USED 0U
170 #endif
171 #else
172 #define __FPU_USED 0U
173 #endif
174
175 #elif defined ( __TASKING__ )
176 #if defined (__FPU_VFP__)
177 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
178 #define __FPU_USED 1U
179 #else
180 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
181 #define __FPU_USED 0U
182 #endif
183 #else
184 #define __FPU_USED 0U
185 #endif
186
187 #elif defined ( __CSMC__ )
188 #if ( __CSMC__ & 0x400U)
189 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
190 #define __FPU_USED 1U
191 #else
192 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
193 #define __FPU_USED 0U
194 #endif
195 #else
196 #define __FPU_USED 0U
197 #endif
198
199 #endif
200
201 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
202
203
204 #ifdef __cplusplus
205 }
206 #endif
207
208 #endif /* __CORE_CM52_H_GENERIC */
209
210 #ifndef __CMSIS_GENERIC
211
212 #ifndef __CORE_CM52_H_DEPENDANT
213 #define __CORE_CM52_H_DEPENDANT
214
215 #ifdef __cplusplus
216 extern "C" {
217 #endif
218
219 /* check device defines and use defaults */
220 #if defined __CHECK_DEVICE_DEFINES
221 #ifndef __CM52_REV
222 #define __CM52_REV 0x0002U
223 #warning "__CM52_REV not defined in device header file; using default!"
224 #endif
225
226 #ifndef __FPU_PRESENT
227 #define __FPU_PRESENT 0U
228 #warning "__FPU_PRESENT not defined in device header file; using default!"
229 #endif
230
231 #if __FPU_PRESENT != 0U
232 #ifndef __FPU_DP
233 #define __FPU_DP 0U
234 #warning "__FPU_DP not defined in device header file; using default!"
235 #endif
236 #endif
237
238 #ifndef __MPU_PRESENT
239 #define __MPU_PRESENT 0U
240 #warning "__MPU_PRESENT not defined in device header file; using default!"
241 #endif
242
243 #ifndef __ICACHE_PRESENT
244 #define __ICACHE_PRESENT 0U
245 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
246 #endif
247
248 #ifndef __DCACHE_PRESENT
249 #define __DCACHE_PRESENT 0U
250 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
251 #endif
252
253 #ifndef __UCACHE_PRESENT
254 #define __UCACHE_PRESENT 0U
255 #warning "__UCACHE_PRESENT not defined in device header file; using default!"
256 #endif
257
258 #ifndef __VTOR_PRESENT
259 #define __VTOR_PRESENT 1U
260 #warning "__VTOR_PRESENT not defined in device header file; using default!"
261 #endif
262
263 #ifndef __PMU_PRESENT
264 #define __PMU_PRESENT 0U
265 #warning "__PMU_PRESENT not defined in device header file; using default!"
266 #endif
267
268 #if __PMU_PRESENT != 0U
269 #ifndef __PMU_NUM_EVENTCNT
270 #define __PMU_NUM_EVENTCNT 8U
271 #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!"
272 #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2)
273 #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */
274 #endif
275 #endif
276
277 #ifndef __SAUREGION_PRESENT
278 #define __SAUREGION_PRESENT 0U
279 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
280 #endif
281
282 #ifndef __DSP_PRESENT
283 #define __DSP_PRESENT 0U
284 #warning "__DSP_PRESENT not defined in device header file; using default!"
285 #endif
286
287 #ifndef __NVIC_PRIO_BITS
288 #define __NVIC_PRIO_BITS 3U
289 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
290 #endif
291
292 #ifndef __Vendor_SysTickConfig
293 #define __Vendor_SysTickConfig 0U
294 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
295 #endif
296 #endif
297
298 /* IO definitions (access restrictions to peripheral registers) */
299 /**
300 \defgroup CMSIS_glob_defs CMSIS Global Defines
301
302 <strong>IO Type Qualifiers</strong> are used
303 \li to specify the access to peripheral variables.
304 \li for automatic generation of peripheral register debug information.
305 */
306 #ifdef __cplusplus
307 #define __I volatile /*!< Defines 'read only' permissions */
308 #else
309 #define __I volatile const /*!< Defines 'read only' permissions */
310 #endif
311 #define __O volatile /*!< Defines 'write only' permissions */
312 #define __IO volatile /*!< Defines 'read / write' permissions */
313
314 /* following defines should be used for structure members */
315 #define __IM volatile const /*! Defines 'read only' structure member permissions */
316 #define __OM volatile /*! Defines 'write only' structure member permissions */
317 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
318
319 /*@} end of group Cortex_M52 */
320
321
322
323 /*******************************************************************************
324 * Register Abstraction
325 Core Register contain:
326 - Core Register
327 - Core NVIC Register
328 - Core EWIC Register
329 - Core EWIC Interrupt Status Access Register
330 - Core SCB Register
331 - Core SysTick Register
332 - Core Debug Register
333 - Core PMU Register
334 - Core MPU Register
335 - Core SAU Register
336 - Core FPU Register
337 ******************************************************************************/
338 /**
339 \defgroup CMSIS_core_register Defines and Type Definitions
340 \brief Type definitions and defines for Cortex-M processor based devices.
341 */
342
343 /**
344 \ingroup CMSIS_core_register
345 \defgroup CMSIS_CORE Status and Control Registers
346 \brief Core Register type definitions.
347 @{
348 */
349
350 /**
351 \brief Union type to access the Application Program Status Register (APSR).
352 */
353 typedef union
354 {
355 struct
356 {
357 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
358 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
359 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
360 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
361 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
362 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
363 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
364 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
365 } b; /*!< Structure used for bit access */
366 uint32_t w; /*!< Type used for word access */
367 } APSR_Type;
368
369 /** \brief APSR Register Definitions */
370 #define APSR_N_Pos 31U /*!< APSR: N Position */
371 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
372
373 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
374 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
375
376 #define APSR_C_Pos 29U /*!< APSR: C Position */
377 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
378
379 #define APSR_V_Pos 28U /*!< APSR: V Position */
380 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
381
382 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
383 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
384
385 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
386 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
387
388
389 /**
390 \brief Union type to access the Interrupt Program Status Register (IPSR).
391 */
392 typedef union
393 {
394 struct
395 {
396 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
397 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
398 } b; /*!< Structure used for bit access */
399 uint32_t w; /*!< Type used for word access */
400 } IPSR_Type;
401
402 /** \brief IPSR Register Definitions */
403 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
404 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
405
406
407 /**
408 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
409 */
410 typedef union
411 {
412 struct
413 {
414 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
415 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
416 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
417 uint32_t _reserved1:1; /*!< bit: 20 Reserved */
418 uint32_t B:1; /*!< bit: 21 BTI active (read 0) */
419 uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */
420 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
421 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
422 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
423 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
424 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
425 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
426 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
427 } b; /*!< Structure used for bit access */
428 uint32_t w; /*!< Type used for word access */
429 } xPSR_Type;
430
431 /** \brief xPSR Register Definitions */
432 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
433 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
434
435 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
436 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
437
438 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
439 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
440
441 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
442 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
443
444 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
445 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
446
447 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
448 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
449
450 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
451 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
452
453 #define xPSR_B_Pos 21U /*!< xPSR: B Position */
454 #define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */
455
456 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
457 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
458
459 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
460 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
461
462
463 /**
464 \brief Union type to access the Control Registers (CONTROL).
465 */
466 typedef union
467 {
468 struct
469 {
470 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
471 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
472 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
473 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
474 uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */
475 uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */
476 uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */
477 uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */
478 uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */
479 } b; /*!< Structure used for bit access */
480 uint32_t w; /*!< Type used for word access */
481 } CONTROL_Type;
482
483 /** \brief CONTROL Register Definitions */
484 #define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */
485 #define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */
486
487 #define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */
488 #define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */
489
490 #define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */
491 #define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */
492
493 #define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */
494 #define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */
495
496 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
497 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
498
499 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
500 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
501
502 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
503 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
504
505 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
506 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
507
508 /*@} end of group CMSIS_CORE */
509
510
511 /**
512 \ingroup CMSIS_core_register
513 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
514 \brief Type definitions for the NVIC Registers
515 @{
516 */
517
518 /**
519 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
520 */
521 typedef struct
522 {
523 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
524 uint32_t RESERVED0[16U];
525 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
526 uint32_t RESERVED1[16U];
527 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
528 uint32_t RESERVED2[16U];
529 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
530 uint32_t RESERVED3[16U];
531 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
532 uint32_t RESERVED4[16U];
533 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
534 uint32_t RESERVED5[16U];
535 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
536 uint32_t RESERVED6[580U];
537 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
538 } NVIC_Type;
539
540 /** \brief NVIC Software Triggered Interrupt Register Definitions */
541 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
542 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
543
544 /*@} end of group CMSIS_NVIC */
545
546
547 /**
548 \ingroup CMSIS_core_register
549 \defgroup CMSIS_SCB System Control Block (SCB)
550 \brief Type definitions for the System Control Block Registers
551 @{
552 */
553
554 /**
555 \brief Structure type to access the System Control Block (SCB).
556 */
557 typedef struct
558 {
559 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
560 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
561 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
562 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
563 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
564 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
565 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
566 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
567 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
568 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
569 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
570 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
571 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
572 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
573 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
574 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
575 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
576 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
577 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
578 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
579 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
580 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
581 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
582 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
583 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
584 uint32_t RESERVED0[21U];
585 __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
586 __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
587 uint32_t RESERVED1[69U];
588 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
589 __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
590 uint32_t RESERVED2[14U];
591 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
592 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
593 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
594 uint32_t RESERVED3[1U];
595 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
596 uint32_t RESERVED4[1U];
597 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
598 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
599 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
600 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
601 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
602 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
603 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
604 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
605 __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
606 } SCB_Type;
607
608 /** \brief SCB CPUID Register Definitions */
609 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
610 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
611
612 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
613 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
614
615 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
616 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
617
618 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
619 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
620
621 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
622 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
623
624 /** \brief SCB Interrupt Control State Register Definitions */
625 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
626 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
627
628 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
629 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
630
631 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
632 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
633
634 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
635 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
636
637 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
638 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
639
640 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
641 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
642
643 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
644 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
645
646 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
647 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
648
649 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
650 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
651
652 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
653 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
654
655 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
656 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
657
658 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
659 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
660
661 /** \brief SCB Vector Table Offset Register Definitions */
662 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
663 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
664
665 /** \brief SCB Application Interrupt and Reset Control Register Definitions */
666 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
667 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
668
669 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
670 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
671
672 #define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */
673 #define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */
674
675 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
676 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
677
678 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
679 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
680
681 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
682 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
683
684 #define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */
685 #define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */
686
687 #define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */
688 #define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */
689
690 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
691 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
692
693 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
694 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
695
696 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
697 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
698
699 /** \brief SCB System Control Register Definitions */
700 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
701 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
702
703 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
704 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
705
706 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
707 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
708
709 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
710 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
711
712 /** \brief SCB Configuration Control Register Definitions */
713 #define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */
714 #define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */
715
716 #define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */
717 #define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */
718
719 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
720 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
721
722 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
723 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
724
725 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
726 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
727
728 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
729 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
730
731 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
732 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
733
734 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
735 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
736
737 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
738 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
739
740 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
741 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
742
743 /** \brief SCB System Handler Control and State Register Definitions */
744 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
745 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
746
747 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
748 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
749
750 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
751 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
752
753 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
754 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
755
756 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
757 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
758
759 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
760 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
761
762 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
763 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
764
765 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
766 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
767
768 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
769 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
770
771 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
772 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
773
774 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
775 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
776
777 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
778 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
779
780 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
781 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
782
783 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
784 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
785
786 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
787 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
788
789 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
790 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
791
792 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
793 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
794
795 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
796 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
797
798 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
799 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
800
801 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
802 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
803
804 /** \brief SCB Configurable Fault Status Register Definitions */
805 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
806 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
807
808 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
809 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
810
811 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
812 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
813
814 /** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */
815 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
816 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
817
818 #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
819 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
820
821 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
822 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
823
824 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
825 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
826
827 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
828 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
829
830 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
831 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
832
833 /** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */
834 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
835 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
836
837 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
838 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
839
840 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
841 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
842
843 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
844 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
845
846 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
847 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
848
849 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
850 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
851
852 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
853 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
854
855 /** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */
856 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
857 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
858
859 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
860 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
861
862 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
863 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
864
865 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
866 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
867
868 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
869 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
870
871 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
872 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
873
874 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
875 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
876
877 /** \brief SCB Hard Fault Status Register Definitions */
878 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
879 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
880
881 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
882 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
883
884 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
885 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
886
887 /** \brief SCB Debug Fault Status Register Definitions */
888 #define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */
889 #define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */
890
891 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
892 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
893
894 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
895 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
896
897 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
898 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
899
900 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
901 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
902
903 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
904 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
905
906 /** \brief SCB Non-Secure Access Control Register Definitions */
907 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
908 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
909
910 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
911 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
912
913 #define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */
914 #define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */
915
916 #define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */
917 #define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */
918
919 #define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */
920 #define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */
921
922 #define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */
923 #define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */
924
925 #define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */
926 #define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */
927
928 #define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */
929 #define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */
930
931 #define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */
932 #define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */
933
934 #define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */
935 #define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */
936
937 /** \brief SCB Debug Feature Register 0 Definitions */
938 #define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */
939 #define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */
940
941 #define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */
942 #define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */
943
944 /** \brief SCB Cache Level ID Register Definitions */
945 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
946 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
947
948 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
949 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
950
951 #define SCB_CLIDR_CTYPE1_Pos 0U
952 #define SCB_CLIDR_CTYPE1_Msk (7UL << SCB_CLIDR_CTYPE1_Pos)
953
954 /** \brief SCB Cache Type Register Definitions */
955 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
956 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
957
958 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
959 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
960
961 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
962 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
963
964 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
965 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
966
967 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
968 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
969
970 /** \brief SCB Cache Size ID Register Definitions */
971 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
972 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
973
974 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
975 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
976
977 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
978 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
979
980 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
981 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
982
983 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
984 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
985
986 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
987 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
988
989 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
990 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
991
992 /** \brief SCB Cache Size Selection Register Definitions */
993 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
994 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
995
996 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
997 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
998
999 /** \brief SCB Software Triggered Interrupt Register Definitions */
1000 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
1001 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
1002
1003 /** \brief SCB RAS Fault Status Register Definitions */
1004 #define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */
1005 #define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */
1006
1007 #define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */
1008 #define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */
1009
1010 #define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */
1011 #define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */
1012
1013 /** \brief SCB D-Cache Invalidate by Set-way Register Definitions */
1014 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
1015 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
1016
1017 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
1018 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
1019
1020 /** \brief SCB D-Cache Clean by Set-way Register Definitions */
1021 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
1022 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
1023
1024 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
1025 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
1026
1027 /** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
1028 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
1029 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
1030
1031 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
1032 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
1033
1034
1035 /** \brief SCB U-Cache Invalidate by Set-way Register Definitions */
1036 #define SCB_DCISW_UC_WAY_Pos 31U /*!< SCB DCISW: Way Position */
1037 #define SCB_DCISW_UC_WAY_Msk (1UL << SCB_DCISW_UC_WAY_Pos) /*!< SCB DCISW: Way Mask */
1038
1039 #define SCB_DCISW_UC_SET_Pos 5U /*!< SCB DCISW: Set Position */
1040 #define SCB_DCISW_UC_SET_Msk (0x3FFUL << SCB_DCISW_UC_SET_Pos) /*!< SCB DCISW: Set Mask */
1041
1042 /** \brief SCB U-Cache Clean by Set-way Register Definitions */
1043 #define SCB_DCCSW_UC_WAY_Pos 31U /*!< SCB DCCSW: Way Position */
1044 #define SCB_DCCSW_UC_WAY_Msk (1UL << SCB_DCCSW_UC_WAY_Pos) /*!< SCB DCCSW: Way Mask */
1045
1046 #define SCB_DCCSW_UC_SET_Pos 5U /*!< SCB DCCSW: Set Position */
1047 #define SCB_DCCSW_UC_SET_Msk (0x3FFUL << SCB_DCCSW_UC_SET_Pos) /*!< SCB DCCSW: Set Mask */
1048
1049 /** \brief SCB U-Cache Clean and Invalidate by Set-way Register Definitions */
1050 #define SCB_DCCISW_UC_WAY_Pos 31U /*!< SCB DCCISW: Way Position */
1051 #define SCB_DCCISW_UC_WAY_Msk (1UL << SCB_DCCISW_UC_WAY_Pos) /*!< SCB DCCISW: Way Mask */
1052
1053 #define SCB_DCCISW_UC_SET_Pos 5U /*!< SCB DCCISW: Set Position */
1054 #define SCB_DCCISW_UC_SET_Msk (0x3FFUL << SCB_DCCISW_UC_SET_Pos) /*!< SCB DCCISW: Set Mask */
1055
1056
1057 /*@} end of group CMSIS_SCB */
1058
1059
1060 /**
1061 \ingroup CMSIS_core_register
1062 \defgroup CMSIS_ICB Implementation Control Block register (ICB)
1063 \brief Type definitions for the Implementation Control Block Register
1064 @{
1065 */
1066
1067 /**
1068 \brief Structure type to access the Implementation Control Block (ICB).
1069 */
1070 typedef struct
1071 {
1072 uint32_t RESERVED0[1U];
1073 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
1074 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
1075 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
1076 } ICB_Type;
1077
1078 /** \brief ICB Auxiliary Control Register Definitions */
1079 #define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */
1080 #define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */
1081
1082 #define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */
1083 #define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */
1084
1085 #define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */
1086 #define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */
1087
1088 #define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */
1089 #define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */
1090
1091 #define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */
1092 #define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */
1093
1094 #define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
1095 #define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
1096
1097 #define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */
1098 #define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */
1099
1100 #define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
1101 #define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
1102
1103 #define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */
1104 #define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */
1105
1106 #define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */
1107 #define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */
1108
1109 #define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */
1110 #define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */
1111
1112 #define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */
1113 #define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */
1114
1115 #define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */
1116 #define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */
1117
1118 #define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
1119 #define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
1120
1121 /** \brief ICB Interrupt Controller Type Register Definitions */
1122 #define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
1123 #define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
1124
1125 /*@} end of group CMSIS_ICB */
1126
1127
1128 /**
1129 \ingroup CMSIS_core_register
1130 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
1131 \brief Type definitions for the System Timer Registers.
1132 @{
1133 */
1134
1135 /**
1136 \brief Structure type to access the System Timer (SysTick).
1137 */
1138 typedef struct
1139 {
1140 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
1141 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
1142 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
1143 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
1144 } SysTick_Type;
1145
1146 /** \brief SysTick Control / Status Register Definitions */
1147 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
1148 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
1149
1150 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
1151 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
1152
1153 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
1154 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1155
1156 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1157 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1158
1159 /** \brief SysTick Reload Register Definitions */
1160 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
1161 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
1162
1163 /** \brief SysTick Current Register Definitions */
1164 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
1165 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
1166
1167 /** \brief SysTick Calibration Register Definitions */
1168 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
1169 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
1170
1171 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
1172 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
1173
1174 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
1175 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
1176
1177 /*@} end of group CMSIS_SysTick */
1178
1179
1180 /**
1181 \ingroup CMSIS_core_register
1182 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
1183 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
1184 @{
1185 */
1186
1187 /**
1188 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1189 */
1190 typedef struct
1191 {
1192 __OM union
1193 {
1194 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */
1195 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */
1196 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */
1197 } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */
1198 uint32_t RESERVED0[864U];
1199 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */
1200 uint32_t RESERVED1[15U];
1201 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */
1202 uint32_t RESERVED2[15U];
1203 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */
1204 uint32_t RESERVED3[27U];
1205 __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */
1206 uint32_t RESERVED4[1U];
1207 __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */
1208 uint32_t RESERVED5[1U];
1209 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */
1210 uint32_t RESERVED6[46U];
1211 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
1212 uint32_t RESERVED7[3U];
1213 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
1214 } ITM_Type;
1215
1216 /** \brief ITM Stimulus Port Register Definitions */
1217 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
1218 #define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
1219
1220 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
1221 #define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
1222
1223 /** \brief ITM Trace Privilege Register Definitions */
1224 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
1225 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
1226
1227 /** \brief ITM Trace Control Register Definitions */
1228 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
1229 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
1230
1231 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
1232 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
1233
1234 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
1235 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
1236
1237 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
1238 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
1239
1240 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
1241 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
1242
1243 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
1244 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
1245
1246 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
1247 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
1248
1249 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
1250 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
1251
1252 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
1253 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
1254
1255 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
1256 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
1257
1258 /** \brief ITM Integration Read Register Definitions */
1259 #define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */
1260 #define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */
1261
1262 #define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */
1263 #define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */
1264
1265 /** \brief ITM Integration Write Register Definitions */
1266 #define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */
1267 #define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */
1268
1269 #define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */
1270 #define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */
1271
1272 /** \brief ITM Integration Mode Control Register Definitions */
1273 #define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */
1274 #define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */
1275
1276 /*@}*/ /* end of group CMSIS_ITM */
1277
1278
1279 /**
1280 \ingroup CMSIS_core_register
1281 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1282 \brief Type definitions for the Data Watchpoint and Trace (DWT)
1283 @{
1284 */
1285
1286 /**
1287 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1288 */
1289 typedef struct
1290 {
1291 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1292 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
1293 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1294 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
1295 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
1296 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1297 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
1298 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
1299 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1300 uint32_t RESERVED1[1U];
1301 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1302 uint32_t RESERVED2[1U];
1303 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
1304 uint32_t RESERVED3[1U];
1305 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1306 __IOM uint32_t VMASK1; /*!< Offset: 0x03C (R/W) Comparator Value Mask 1 */
1307 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
1308 uint32_t RESERVED4[1U];
1309 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1310 uint32_t RESERVED5[1U];
1311 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
1312 uint32_t RESERVED6[1U];
1313 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1314 __IOM uint32_t VMASK3; /*!< Offset: 0x05C (R/W) Comparator Value Mask 3 */
1315 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
1316 uint32_t RESERVED7[1U];
1317 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
1318 uint32_t RESERVED8[1U];
1319 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
1320 uint32_t RESERVED9[1U];
1321 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
1322 uint32_t RESERVED10[1U];
1323 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
1324 uint32_t RESERVED11[1U];
1325 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
1326 uint32_t RESERVED12[1U];
1327 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
1328 uint32_t RESERVED13[1U];
1329 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
1330 uint32_t RESERVED14[968U];
1331 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */
1332 uint32_t RESERVED15[3U];
1333 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
1334 } DWT_Type;
1335
1336 /** \brief DWT Control Register Definitions */
1337 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
1338 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
1339
1340 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
1341 #define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
1342
1343 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
1344 #define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
1345
1346 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
1347 #define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
1348
1349 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
1350 #define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
1351
1352 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
1353 #define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
1354
1355 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
1356 #define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
1357
1358 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
1359 #define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
1360
1361 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
1362 #define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
1363
1364 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
1365 #define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
1366
1367 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
1368 #define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
1369
1370 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
1371 #define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
1372
1373 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
1374 #define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
1375
1376 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
1377 #define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
1378
1379 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
1380 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
1381
1382 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
1383 #define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
1384
1385 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
1386 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
1387
1388 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
1389 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
1390
1391 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
1392 #define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
1393
1394 /** \brief DWT CPI Count Register Definitions */
1395 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
1396 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1397
1398 /** \brief DWT Exception Overhead Count Register Definitions */
1399 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1400 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1401
1402 /** \brief DWT Sleep Count Register Definitions */
1403 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1404 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1405
1406 /** \brief DWT LSU Count Register Definitions */
1407 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1408 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1409
1410 /** \brief DWT Folded-instruction Count Register Definitions */
1411 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1412 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1413
1414 /** \brief DWT Comparator Function Register Definitions */
1415 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
1416 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
1417
1418 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1419 #define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1420
1421 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1422 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1423
1424 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
1425 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
1426
1427 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
1428 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
1429
1430 /*@}*/ /* end of group CMSIS_DWT */
1431
1432
1433 /**
1434 \ingroup CMSIS_core_register
1435 \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED)
1436 \brief Type definitions for the Memory System Control Registers (MEMSYSCTL)
1437 @{
1438 */
1439
1440 /**
1441 \brief Structure type to access the Memory System Control Registers (MEMSYSCTL).
1442 */
1443 typedef struct
1444 {
1445 __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */
1446 uint32_t RESERVED1[3U];
1447 __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */
1448 __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */
1449 __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */
1450 uint32_t RESERVED2[313U];
1451 __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */
1452 __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */
1453 uint32_t RESERVED3[2U];
1454 __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */
1455 uint32_t RESERVED4[44U];
1456 __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */
1457 __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */
1458 uint32_t RESERVED5[2U];
1459 __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */
1460 } MemSysCtl_Type;
1461
1462 /** \brief MemSysCtl Memory System Control Register Definitions */
1463 #define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */
1464 #define MEMSYSCTL_MSCR_CPWRDN_Msk (1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */
1465
1466 #define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */
1467 #define MEMSYSCTL_MSCR_DCCLEAN_Msk (1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */
1468
1469 #define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */
1470 #define MEMSYSCTL_MSCR_ICACTIVE_Msk (1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */
1471
1472 #define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */
1473 #define MEMSYSCTL_MSCR_DCACTIVE_Msk (1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */
1474
1475 #define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */
1476 #define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */
1477
1478 #define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */
1479 #define MEMSYSCTL_MSCR_EVECCFAULT_Msk (1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */
1480
1481 #define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */
1482 #define MEMSYSCTL_MSCR_FORCEWT_Msk (1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */
1483
1484 #define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */
1485 #define MEMSYSCTL_MSCR_ECCEN_Msk (1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */
1486
1487 /** \brief MemSysCtl ITCM Control Register Definitions */
1488 #define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */
1489 #define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */
1490
1491 #define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */
1492 #define MEMSYSCTL_ITCMCR_EN_Msk (1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */
1493
1494 /** \brief MemSysCtl DTCM Control Register Definitions */
1495 #define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */
1496 #define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */
1497
1498 #define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */
1499 #define MEMSYSCTL_DTCMCR_EN_Msk (1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */
1500
1501 /** \brief MemSysCtl P-AHB Control Register Definitions */
1502 #define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */
1503 #define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */
1504
1505 #define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */
1506 #define MEMSYSCTL_PAHBCR_EN_Msk (1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */
1507
1508 /** \brief MemSysCtl ITGU Control Register Definitions */
1509 #define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */
1510 #define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */
1511
1512 #define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */
1513 #define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */
1514
1515 /** \brief MemSysCtl ITGU Configuration Register Definitions */
1516 #define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */
1517 #define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */
1518
1519 #define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */
1520 #define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */
1521
1522 #define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */
1523 #define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */
1524
1525 /** \brief MemSysCtl DTGU Control Registers Definitions */
1526 #define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */
1527 #define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */
1528
1529 #define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */
1530 #define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */
1531
1532 /** \brief MemSysCtl DTGU Configuration Register Definitions */
1533 #define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */
1534 #define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */
1535
1536 #define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */
1537 #define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */
1538
1539 #define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */
1540 #define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */
1541
1542 /*@}*/ /* end of group MemSysCtl_Type */
1543
1544
1545 /**
1546 \ingroup CMSIS_core_register
1547 \defgroup DCAR_Type Direct Cache Access Registers
1548 \brief Type definitions for the Direct Cache Access Registers (DCAR)
1549 @{
1550 */
1551
1552 /**
1553 \brief Structure type to access the Direct Cache Access Registers (DCAR).
1554 */
1555 typedef struct
1556 {
1557 __IM uint32_t DCADCRR; /*!< Offset: 0x000 (R/W) Direct Cache Access Data Cache Read Register */
1558 __IM uint32_t DCAICRR; /*!< Offset: 0x004 (R/W) Direct Cache Access Instruction Cache Read Register */
1559 uint32_t RESERVED1[2];
1560 __IOM uint32_t DCADCLR; /*!< Offset: 0x010 (R/W) Direct Cache Access Data Cache Location Registers */
1561 __IOM uint32_t DCAICLR; /*!< Offset: 0x014 (R/W) Direct Cache Access Instruction Cache Location Registers */
1562 } DCAR_Type;
1563
1564 /*@}*/ /* end of group DCAR_Type */
1565
1566
1567 /**
1568 \ingroup CMSIS_core_register
1569 \defgroup PwrModCtl_Type Power Mode Control Registers
1570 \brief Type definitions for the Power Mode Control Registers (PWRMODCTL)
1571 @{
1572 */
1573
1574 /**
1575 \brief Structure type to access the Power Mode Control Registers (PWRMODCTL).
1576 */
1577 typedef struct
1578 {
1579 __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */
1580 __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */
1581 } PwrModCtl_Type;
1582
1583 /** \brief PwrModCtl Core Power Domain Low Power State Register Definitions */
1584 #define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */
1585 #define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */
1586
1587 #define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */
1588 #define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */
1589
1590 /** \brief PwrModCtl Debug Power Domain Low Power State Register Definitions */
1591 #define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */
1592 #define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */
1593
1594 /*@}*/ /* end of group PwrModCtl_Type */
1595
1596
1597 /**
1598 \ingroup CMSIS_core_register
1599 \defgroup EWIC_Type External Wakeup Interrupt Controller Registers
1600 \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC)
1601 @{
1602 */
1603
1604 /**
1605 \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC).
1606 */
1607 typedef struct
1608 {
1609 __IOM uint32_t EWIC_CR; /*!< Offset: 0x000 (R/W) EWIC Control Register */
1610 __IOM uint32_t EWIC_ASCR; /*!< Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register */
1611 __OM uint32_t EWIC_CLRMASK; /*!< Offset: 0x008 ( /W) EWIC Clear Mask Register */
1612 __IM uint32_t EWIC_NUMID; /*!< Offset: 0x00C (R/ ) EWIC Event Number ID Register */
1613 uint32_t RESERVED0[124U];
1614 __IOM uint32_t EWIC_MASKA; /*!< Offset: 0x200 (R/W) EWIC MaskA Register */
1615 __IOM uint32_t EWIC_MASKn[15]; /*!< Offset: 0x204 (R/W) EWIC Maskn Registers */
1616 uint32_t RESERVED1[112U];
1617 __IM uint32_t EWIC_PENDA; /*!< Offset: 0x400 (R/ ) EWIC PendA Event Register */
1618 __IOM uint32_t EWIC_PENDn[15]; /*!< Offset: 0x404 (R/W) EWIC Pendn Event Registers */
1619 uint32_t RESERVED2[112U];
1620 __IM uint32_t EWIC_PSR; /*!< Offset: 0x600 (R/ ) EWIC Pend Summary Register */
1621 } EWIC_Type;
1622
1623 /** \brief EWIC Control Register Definitions */
1624 #define EWIC_EWIC_CR_EN_Pos 0U /*!< EWIC EWIC_CR: EN Position */
1625 #define EWIC_EWIC_CR_EN_Msk (1UL /*<< EWIC_EWIC_CR_EN_Pos*/) /*!< EWIC EWIC_CR: EN Mask */
1626
1627 /** \brief EWIC Automatic Sequence Control Register Definitions */
1628 #define EWIC_EWIC_ASCR_ASPU_Pos 1U /*!< EWIC EWIC_ASCR: ASPU Position */
1629 #define EWIC_EWIC_ASCR_ASPU_Msk (1UL << EWIC_EWIC_ASCR_ASPU_Pos) /*!< EWIC EWIC_ASCR: ASPU Mask */
1630
1631 #define EWIC_EWIC_ASCR_ASPD_Pos 0U /*!< EWIC EWIC_ASCR: ASPD Position */
1632 #define EWIC_EWIC_ASCR_ASPD_Msk (1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/) /*!< EWIC EWIC_ASCR: ASPD Mask */
1633
1634 /** \brief EWIC Event Number ID Register Definitions */
1635 #define EWIC_EWIC_NUMID_NUMEVENT_Pos 0U /*!< EWIC_NUMID: NUMEVENT Position */
1636 #define EWIC_EWIC_NUMID_NUMEVENT_Msk (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/) /*!< EWIC_NUMID: NUMEVENT Mask */
1637
1638 /** \brief EWIC Mask A Register Definitions */
1639 #define EWIC_EWIC_MASKA_EDBGREQ_Pos 2U /*!< EWIC EWIC_MASKA: EDBGREQ Position */
1640 #define EWIC_EWIC_MASKA_EDBGREQ_Msk (1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos) /*!< EWIC EWIC_MASKA: EDBGREQ Mask */
1641
1642 #define EWIC_EWIC_MASKA_NMI_Pos 1U /*!< EWIC EWIC_MASKA: NMI Position */
1643 #define EWIC_EWIC_MASKA_NMI_Msk (1UL << EWIC_EWIC_MASKA_NMI_Pos) /*!< EWIC EWIC_MASKA: NMI Mask */
1644
1645 #define EWIC_EWIC_MASKA_EVENT_Pos 0U /*!< EWIC EWIC_MASKA: EVENT Position */
1646 #define EWIC_EWIC_MASKA_EVENT_Msk (1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/) /*!< EWIC EWIC_MASKA: EVENT Mask */
1647
1648 /** \brief EWIC Mask n Register Definitions */
1649 #define EWIC_EWIC_MASKn_IRQ_Pos 0U /*!< EWIC EWIC_MASKn: IRQ Position */
1650 #define EWIC_EWIC_MASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/) /*!< EWIC EWIC_MASKn: IRQ Mask */
1651
1652 /** \brief EWIC Pend A Register Definitions */
1653 #define EWIC_EWIC_PENDA_EDBGREQ_Pos 2U /*!< EWIC EWIC_PENDA: EDBGREQ Position */
1654 #define EWIC_EWIC_PENDA_EDBGREQ_Msk (1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos) /*!< EWIC EWIC_PENDA: EDBGREQ Mask */
1655
1656 #define EWIC_EWIC_PENDA_NMI_Pos 1U /*!< EWIC EWIC_PENDA: NMI Position */
1657 #define EWIC_EWIC_PENDA_NMI_Msk (1UL << EWIC_EWIC_PENDA_NMI_Pos) /*!< EWIC EWIC_PENDA: NMI Mask */
1658
1659 #define EWIC_EWIC_PENDA_EVENT_Pos 0U /*!< EWIC EWIC_PENDA: EVENT Position */
1660 #define EWIC_EWIC_PENDA_EVENT_Msk (1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/) /*!< EWIC EWIC_PENDA: EVENT Mask */
1661
1662 /** \brief EWIC Pend n Register Definitions */
1663 #define EWIC_EWIC_PENDn_IRQ_Pos 0U /*!< EWIC EWIC_PENDn: IRQ Position */
1664 #define EWIC_EWIC_PENDn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/) /*!< EWIC EWIC_PENDn: IRQ Mask */
1665
1666 /** \brief EWIC Pend Summary Register Definitions */
1667 #define EWIC_EWIC_PSR_NZ_Pos 1U /*!< EWIC EWIC_PSR: NZ Position */
1668 #define EWIC_EWIC_PSR_NZ_Msk (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos) /*!< EWIC EWIC_PSR: NZ Mask */
1669
1670 #define EWIC_EWIC_PSR_NZA_Pos 0U /*!< EWIC EWIC_PSR: NZA Position */
1671 #define EWIC_EWIC_PSR_NZA_Msk (1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/) /*!< EWIC EWIC_PSR: NZA Mask */
1672
1673 /*@}*/ /* end of group EWIC_Type */
1674
1675
1676 /**
1677 \ingroup CMSIS_core_register
1678 \defgroup EWIC_ISA_Type External Wakeup Interrupt Controller (EWIC) interrupt status access registers
1679 \brief Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA)
1680 @{
1681 */
1682
1683 /**
1684 \brief Structure type to access the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA).
1685 */
1686 typedef struct
1687 {
1688 __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */
1689 uint32_t RESERVED0[31U];
1690 __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/ ) Event Mask A Register */
1691 __IM uint32_t EVENTMASKn[15]; /*!< Offset: 0x084 (R/ ) Event Mask Register */
1692 } EWIC_ISA_Type;
1693
1694 /** \brief EWIC_ISA Event Set Pending Register Definitions */
1695 #define EWIC_ISA_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTSPR: EDBGREQ Position */
1696 #define EWIC_ISA_EVENTSPR_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos) /*!< EWIC_ISA EVENTSPR: EDBGREQ Mask */
1697
1698 #define EWIC_ISA_EVENTSPR_NMI_Pos 1U /*!< EWIC_ISA EVENTSPR: NMI Position */
1699 #define EWIC_ISA_EVENTSPR_NMI_Msk (1UL << EWIC_ISA_EVENTSPR_NMI_Pos) /*!< EWIC_ISA EVENTSPR: NMI Mask */
1700
1701 #define EWIC_ISA_EVENTSPR_EVENT_Pos 0U /*!< EWIC_ISA EVENTSPR: EVENT Position */
1702 #define EWIC_ISA_EVENTSPR_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/) /*!< EWIC_ISA EVENTSPR: EVENT Mask */
1703
1704 /** \brief EWIC_ISA Event Mask A Register Definitions */
1705 #define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTMASKA: EDBGREQ Position */
1706 #define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk (1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC_ISA EVENTMASKA: EDBGREQ Mask */
1707
1708 #define EWIC_ISA_EVENTMASKA_NMI_Pos 1U /*!< EWIC_ISA EVENTMASKA: NMI Position */
1709 #define EWIC_ISA_EVENTMASKA_NMI_Msk (1UL << EWIC_ISA_EVENTMASKA_NMI_Pos) /*!< EWIC_ISA EVENTMASKA: NMI Mask */
1710
1711 #define EWIC_ISA_EVENTMASKA_EVENT_Pos 0U /*!< EWIC_ISA EVENTMASKA: EVENT Position */
1712 #define EWIC_ISA_EVENTMASKA_EVENT_Msk (1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/) /*!< EWIC_ISA EVENTMASKA: EVENT Mask */
1713
1714 /** \brief EWIC_ISA Event Mask n Register Definitions */
1715 #define EWIC_ISA_EVENTMASKn_IRQ_Pos 0U /*!< EWIC_ISA EVENTMASKn: IRQ Position */
1716 #define EWIC_ISA_EVENTMASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/) /*!< EWIC_ISA EVENTMASKn: IRQ Mask */
1717
1718 /*@}*/ /* end of group EWIC_ISA_Type */
1719
1720
1721 /**
1722 \ingroup CMSIS_core_register
1723 \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED)
1724 \brief Type definitions for the Error Banking Registers (ERRBNK)
1725 @{
1726 */
1727
1728 /**
1729 \brief Structure type to access the Error Banking Registers (ERRBNK).
1730 */
1731 typedef struct
1732 {
1733 __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */
1734 __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */
1735 uint32_t RESERVED0[2U];
1736 __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */
1737 __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */
1738 uint32_t RESERVED1[2U];
1739 __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */
1740 __IM uint32_t TEBRDATA0; /*!< Offset: 0x024 (RO) Storage for corrected data that is associated with an error.*/
1741 __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */
1742 __IM uint32_t TEBRDATA1; /*!< Offset: 0x02c (RO) Storage for corrected data that is associated with an error.*/
1743 } ErrBnk_Type;
1744
1745 /** \brief ErrBnk Instruction Cache Error Bank Register 0 Definitions */
1746 #define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */
1747 #define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */
1748
1749 #define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */
1750 #define ERRBNK_IEBR0_BANK_Msk (1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */
1751
1752 #define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */
1753 #define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */
1754
1755 #define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */
1756 #define ERRBNK_IEBR0_LOCKED_Msk (1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */
1757
1758 #define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */
1759 #define ERRBNK_IEBR0_VALID_Msk (1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */
1760
1761 /** \brief ErrBnk Instruction Cache Error Bank Register 1 Definitions */
1762 #define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */
1763 #define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */
1764
1765 #define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */
1766 #define ERRBNK_IEBR1_BANK_Msk (1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */
1767
1768 #define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */
1769 #define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */
1770
1771 #define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */
1772 #define ERRBNK_IEBR1_LOCKED_Msk (1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */
1773
1774 #define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */
1775 #define ERRBNK_IEBR1_VALID_Msk (1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */
1776
1777 /** \brief ErrBnk Data Cache Error Bank Register 0 Definitions */
1778 #define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */
1779 #define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */
1780
1781 #define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */
1782 #define ERRBNK_DEBR0_TYPE_Msk (1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */
1783
1784 #define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */
1785 #define ERRBNK_DEBR0_BANK_Msk (1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */
1786
1787 #define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */
1788 #define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */
1789
1790 #define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */
1791 #define ERRBNK_DEBR0_LOCKED_Msk (1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */
1792
1793 #define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */
1794 #define ERRBNK_DEBR0_VALID_Msk (1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */
1795
1796 /** \brief ErrBnk Data Cache Error Bank Register 1 Definitions */
1797 #define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */
1798 #define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */
1799
1800 #define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */
1801 #define ERRBNK_DEBR1_TYPE_Msk (1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */
1802
1803 #define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */
1804 #define ERRBNK_DEBR1_BANK_Msk (1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */
1805
1806 #define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */
1807 #define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */
1808
1809 #define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */
1810 #define ERRBNK_DEBR1_LOCKED_Msk (1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */
1811
1812 #define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */
1813 #define ERRBNK_DEBR1_VALID_Msk (1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */
1814
1815 /** \brief ErrBnk TCM Error Bank Register 0 Definitions */
1816 #define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */
1817 #define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */
1818
1819 #define ERRBNK_TEBR0_POISON_Pos 27U /*!< ERRBNK TEBR0: POISON Position */
1820 #define ERRBNK_TEBR0_POISON_Msk (1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */
1821
1822 #define ERRBNK_TEBR0_TYPE_Pos 26U /*!< ERRBNK TEBR0: TYPE Position */
1823 #define ERRBNK_TEBR0_TYPE_Msk (1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */
1824
1825 #define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */
1826 #define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */
1827
1828 #define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */
1829 #define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */
1830
1831 #define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */
1832 #define ERRBNK_TEBR0_LOCKED_Msk (1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */
1833
1834 #define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */
1835 #define ERRBNK_TEBR0_VALID_Msk (1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */
1836
1837 /** \brief ErrBnk TCM Error Bank Register 1 Definitions */
1838 #define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */
1839 #define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */
1840
1841 #define ERRBNK_TEBR1_POISON_Pos 27U /*!< ERRBNK TEBR1: POISON Position */
1842 #define ERRBNK_TEBR1_POISON_Msk (1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */
1843
1844 #define ERRBNK_TEBR1_TYPE_Pos 26U /*!< ERRBNK TEBR1: TYPE Position */
1845 #define ERRBNK_TEBR1_TYPE_Msk (1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */
1846
1847 #define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */
1848 #define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */
1849
1850 #define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */
1851 #define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */
1852
1853 #define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */
1854 #define ERRBNK_TEBR1_LOCKED_Msk (1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */
1855
1856 #define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */
1857 #define ERRBNK_TEBR1_VALID_Msk (1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */
1858
1859 /*@}*/ /* end of group ErrBnk_Type */
1860
1861
1862 /**
1863 \ingroup CMSIS_core_register
1864 \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED)
1865 \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF)
1866 @{
1867 */
1868
1869 /**
1870 \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF).
1871 */
1872 typedef struct
1873 {
1874 __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */
1875 __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */
1876 } PrcCfgInf_Type;
1877
1878 /** \brief PrcCfgInf Processor Configuration Information Selection Register Definitions */
1879
1880 /** \brief PrcCfgInf Processor Configuration Information Read Data Register Definitions */
1881
1882 /*@}*/ /* end of group PrcCfgInf_Type */
1883
1884
1885 /**
1886 \ingroup CMSIS_core_register
1887 \defgroup STL_Type Software Test Library Observation Registers
1888 \brief Type definitions for the Software Test Library Observation Registerss (STL)
1889 @{
1890 */
1891
1892 /**
1893 \brief Structure type to access the Software Test Library Observation Registerss (STL).
1894 */
1895 typedef struct
1896 {
1897 __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */
1898 __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */
1899 uint32_t RESERVED0[2U];
1900 __IOM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sample Register */
1901 __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */
1902 __IM uint32_t STLDMPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register */
1903
1904 } STL_Type;
1905
1906 /** \brief STL NVIC Pending Priority Tree Register Definitions */
1907 #define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */
1908 #define STL_STLNVICPENDOR_VALID_Msk (1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */
1909
1910 #define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */
1911 #define STL_STLNVICPENDOR_TARGET_Msk (1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */
1912
1913 #define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */
1914 #define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */
1915
1916 #define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */
1917 #define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */
1918
1919 /** \brief STL NVIC Active Priority Tree Register Definitions */
1920 #define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */
1921 #define STL_STLNVICACTVOR_VALID_Msk (1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */
1922
1923 #define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */
1924 #define STL_STLNVICACTVOR_TARGET_Msk (1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */
1925
1926 #define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */
1927 #define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */
1928
1929 #define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */
1930 #define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */
1931
1932 /** \brief STL MPU Sample Register Definitions */
1933 #define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */
1934 #define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */
1935
1936 #define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */
1937 #define STL_STLIDMPUSR_INSTR_Msk (1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */
1938
1939 #define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */
1940 #define STL_STLIDMPUSR_DATA_Msk (1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */
1941
1942 /** \brief STL MPU Region Hit Register Definitions */
1943 #define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */
1944 #define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */
1945
1946 #define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */
1947 #define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */
1948
1949 /** \brief STL MPU Memory Attributes Register Definitions */
1950 #define STL_STLDMPUOR_HITREGION_Pos 9U /*!< STL STLDMPUOR: HITREGION Position */
1951 #define STL_STLDMPUOR_HITREGION_Msk (0xFFUL << STL_STLDMPUOR_HITREGION_Pos) /*!< STL STLDMPUOR: HITREGION Mask */
1952
1953 #define STL_STLDMPUOR_ATTR_Pos 0U /*!< STL STLDMPUOR: ATTR Position */
1954 #define STL_STLDMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLDMPUOR_ATTR_Pos*/) /*!< STL STLDMPUOR: ATTR Mask */
1955
1956 /*@}*/ /* end of group STL_Type */
1957
1958
1959 /**
1960 \ingroup CMSIS_core_register
1961 \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU)
1962 \brief Type definitions for the Trace Port Interface Unit (TPIU)
1963 @{
1964 */
1965
1966 /**
1967 \brief Structure type to access the Trace Port Interface Unit Register (TPIU).
1968 */
1969 typedef struct
1970 {
1971 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1972 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1973 uint32_t RESERVED0[2U];
1974 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1975 uint32_t RESERVED1[55U];
1976 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1977 uint32_t RESERVED2[131U];
1978 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1979 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1980 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
1981 uint32_t RESERVED3[759U];
1982 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1983 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
1984 __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
1985 uint32_t RESERVED4[1U];
1986 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
1987 __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
1988 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1989 uint32_t RESERVED5[39U];
1990 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1991 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1992 uint32_t RESERVED7[8U];
1993 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
1994 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
1995 } TPIU_Type;
1996
1997 /** \brief TPIU Asynchronous Clock Prescaler Register Definitions */
1998 #define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */
1999 #define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */
2000
2001 /** \brief TPIU Selected Pin Protocol Register Definitions */
2002 #define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */
2003 #define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */
2004
2005 /** \brief TPIU Formatter and Flush Status Register Definitions */
2006 #define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */
2007 #define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */
2008
2009 #define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */
2010 #define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */
2011
2012 #define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */
2013 #define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */
2014
2015 #define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */
2016 #define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */
2017
2018 /** \brief TPIU Formatter and Flush Control Register Definitions */
2019 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */
2020 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */
2021
2022 #define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */
2023 #define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */
2024
2025 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */
2026 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
2027
2028 /** \brief TPIU Periodic Synchronization Control Register Definitions */
2029 #define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */
2030 #define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */
2031
2032 /** \brief TPIU TRIGGER Register Definitions */
2033 #define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */
2034 #define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */
2035
2036 /** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */
2037 #define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */
2038 #define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */
2039
2040 #define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */
2041 #define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */
2042
2043 #define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */
2044 #define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */
2045
2046 #define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */
2047 #define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */
2048
2049 #define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */
2050 #define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */
2051
2052 #define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */
2053 #define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */
2054
2055 #define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */
2056 #define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */
2057
2058 /** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */
2059 #define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */
2060 #define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */
2061
2062 #define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */
2063 #define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */
2064
2065 #define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */
2066 #define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */
2067
2068 #define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */
2069 #define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */
2070
2071 /** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */
2072 #define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */
2073 #define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */
2074
2075 #define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */
2076 #define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */
2077
2078 #define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */
2079 #define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */
2080
2081 #define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */
2082 #define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */
2083
2084 #define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */
2085 #define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */
2086
2087 #define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */
2088 #define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */
2089
2090 #define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */
2091 #define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */
2092
2093 /** \brief TPIU Integration Test ATB Control Register 0 Definitions */
2094 #define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */
2095 #define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */
2096
2097 #define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */
2098 #define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */
2099
2100 #define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */
2101 #define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */
2102
2103 #define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */
2104 #define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */
2105
2106 /** \brief TPIU Integration Mode Control Register Definitions */
2107 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */
2108 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
2109
2110 /** \brief TPIU Claim Tag Set Register Definitions */
2111 #define TPIU_CLAIMSET_SET_Pos 0U /*!< TPIU CLAIMSET: SET Position */
2112 #define TPIU_CLAIMSET_SET_Msk (0xFUL /*<< TPIU_CLAIMSET_SET_Pos*/) /*!< TPIU CLAIMSET: SET Mask */
2113
2114 /** \brief TPIU Claim Tag Clear Register Definitions */
2115 #define TPIU_CLAIMCLR_CLR_Pos 0U /*!< TPIU CLAIMCLR: CLR Position */
2116 #define TPIU_CLAIMCLR_CLR_Msk (0xFUL /*<< TPIU_CLAIMCLR_CLR_Pos*/) /*!< TPIU CLAIMCLR: CLR Mask */
2117
2118 /** \brief TPIU DEVID Register Definitions */
2119 #define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */
2120 #define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */
2121
2122 #define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */
2123 #define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */
2124
2125 #define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */
2126 #define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */
2127
2128 #define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */
2129 #define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */
2130
2131 #define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */
2132 #define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */
2133
2134 /** \brief TPIU DEVTYPE Register Definitions */
2135 #define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */
2136 #define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */
2137
2138 #define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */
2139 #define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */
2140
2141 /*@}*/ /* end of group CMSIS_TPIU */
2142
2143
2144 #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
2145 /**
2146 \ingroup CMSIS_core_register
2147 \defgroup CMSIS_PMU Performance Monitoring Unit (PMU)
2148 \brief Type definitions for the Performance Monitoring Unit (PMU)
2149 @{
2150 */
2151
2152 /**
2153 \brief Structure type to access the Performance Monitoring Unit (PMU).
2154 */
2155 typedef struct
2156 {
2157 __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) Event Counter Registers */
2158 #if __PMU_NUM_EVENTCNT<31
2159 uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];
2160 #endif
2161 __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) Cycle Counter Register */
2162 uint32_t RESERVED1[224];
2163 __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) Event Type and Filter Registers */
2164 #if __PMU_NUM_EVENTCNT<31
2165 uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];
2166 #endif
2167 __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) Cycle Counter Filter Register */
2168 uint32_t RESERVED3[480];
2169 __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) Count Enable Set Register */
2170 uint32_t RESERVED4[7];
2171 __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) Count Enable Clear Register */
2172 uint32_t RESERVED5[7];
2173 __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) Interrupt Enable Set Register */
2174 uint32_t RESERVED6[7];
2175 __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) Interrupt Enable Clear Register */
2176 uint32_t RESERVED7[7];
2177 __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) Overflow Flag Status Clear Register */
2178 uint32_t RESERVED8[7];
2179 __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) Software Increment Register */
2180 uint32_t RESERVED9[7];
2181 __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) Overflow Flag Status Set Register */
2182 uint32_t RESERVED10[79];
2183 __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) Type Register */
2184 __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */
2185 uint32_t RESERVED11[108];
2186 __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) Authentication Status Register */
2187 __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) Device Architecture Register */
2188 uint32_t RESERVED12[3];
2189 __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) Device Type Register */
2190 } PMU_Type;
2191
2192 /** \brief PMU Event Counter Registers (0-30) Definitions */
2193 #define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */
2194 #define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */
2195
2196 /** \brief PMU Event Type and Filter Registers (0-30) Definitions */
2197 #define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */
2198 #define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */
2199
2200 /** \brief PMU Count Enable Set Register Definitions */
2201 #define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */
2202 #define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */
2203
2204 #define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */
2205 #define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */
2206
2207 #define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */
2208 #define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */
2209
2210 #define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */
2211 #define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */
2212
2213 #define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */
2214 #define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */
2215
2216 #define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */
2217 #define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */
2218
2219 #define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */
2220 #define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */
2221
2222 #define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */
2223 #define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */
2224
2225 #define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */
2226 #define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */
2227
2228 #define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */
2229 #define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */
2230
2231 #define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */
2232 #define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */
2233
2234 #define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */
2235 #define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */
2236
2237 #define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */
2238 #define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */
2239
2240 #define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */
2241 #define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */
2242
2243 #define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */
2244 #define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */
2245
2246 #define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */
2247 #define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */
2248
2249 #define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */
2250 #define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */
2251
2252 #define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */
2253 #define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */
2254
2255 #define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */
2256 #define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */
2257
2258 #define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */
2259 #define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */
2260
2261 #define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */
2262 #define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */
2263
2264 #define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */
2265 #define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */
2266
2267 #define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */
2268 #define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */
2269
2270 #define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */
2271 #define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */
2272
2273 #define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */
2274 #define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */
2275
2276 #define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */
2277 #define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */
2278
2279 #define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */
2280 #define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */
2281
2282 #define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */
2283 #define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */
2284
2285 #define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */
2286 #define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */
2287
2288 #define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */
2289 #define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */
2290
2291 #define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */
2292 #define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */
2293
2294 #define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */
2295 #define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */
2296
2297 /** \brief PMU Count Enable Clear Register Definitions */
2298 #define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */
2299 #define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */
2300
2301 #define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */
2302 #define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */
2303
2304 #define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */
2305 #define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */
2306
2307 #define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */
2308 #define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */
2309
2310 #define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */
2311 #define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */
2312
2313 #define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */
2314 #define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */
2315
2316 #define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */
2317 #define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */
2318
2319 #define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */
2320 #define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */
2321
2322 #define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */
2323 #define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */
2324
2325 #define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */
2326 #define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */
2327
2328 #define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */
2329 #define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */
2330
2331 #define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */
2332 #define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */
2333
2334 #define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */
2335 #define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */
2336
2337 #define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */
2338 #define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */
2339
2340 #define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */
2341 #define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */
2342
2343 #define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */
2344 #define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */
2345
2346 #define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */
2347 #define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */
2348
2349 #define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */
2350 #define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */
2351
2352 #define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */
2353 #define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */
2354
2355 #define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */
2356 #define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */
2357
2358 #define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */
2359 #define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */
2360
2361 #define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */
2362 #define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */
2363
2364 #define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */
2365 #define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */
2366
2367 #define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */
2368 #define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */
2369
2370 #define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */
2371 #define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */
2372
2373 #define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */
2374 #define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */
2375
2376 #define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */
2377 #define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */
2378
2379 #define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */
2380 #define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */
2381
2382 #define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */
2383 #define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */
2384
2385 #define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */
2386 #define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */
2387
2388 #define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */
2389 #define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */
2390
2391 #define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */
2392 #define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */
2393
2394 /** \brief PMU Interrupt Enable Set Register Definitions */
2395 #define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */
2396 #define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */
2397
2398 #define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */
2399 #define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */
2400
2401 #define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */
2402 #define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */
2403
2404 #define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */
2405 #define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */
2406
2407 #define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */
2408 #define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */
2409
2410 #define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */
2411 #define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */
2412
2413 #define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */
2414 #define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */
2415
2416 #define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */
2417 #define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */
2418
2419 #define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */
2420 #define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */
2421
2422 #define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */
2423 #define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */
2424
2425 #define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */
2426 #define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */
2427
2428 #define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */
2429 #define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */
2430
2431 #define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */
2432 #define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */
2433
2434 #define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */
2435 #define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */
2436
2437 #define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */
2438 #define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */
2439
2440 #define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */
2441 #define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */
2442
2443 #define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */
2444 #define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */
2445
2446 #define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */
2447 #define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */
2448
2449 #define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */
2450 #define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */
2451
2452 #define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */
2453 #define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */
2454
2455 #define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */
2456 #define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */
2457
2458 #define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */
2459 #define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */
2460
2461 #define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */
2462 #define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */
2463
2464 #define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */
2465 #define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */
2466
2467 #define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */
2468 #define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */
2469
2470 #define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */
2471 #define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */
2472
2473 #define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */
2474 #define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */
2475
2476 #define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */
2477 #define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */
2478
2479 #define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */
2480 #define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */
2481
2482 #define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */
2483 #define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */
2484
2485 #define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */
2486 #define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */
2487
2488 #define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */
2489 #define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */
2490
2491 /** \brief PMU Interrupt Enable Clear Register Definitions */
2492 #define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */
2493 #define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */
2494
2495 #define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */
2496 #define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */
2497
2498 #define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */
2499 #define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */
2500
2501 #define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */
2502 #define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */
2503
2504 #define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */
2505 #define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */
2506
2507 #define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */
2508 #define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */
2509
2510 #define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */
2511 #define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */
2512
2513 #define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */
2514 #define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */
2515
2516 #define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */
2517 #define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */
2518
2519 #define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */
2520 #define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */
2521
2522 #define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */
2523 #define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */
2524
2525 #define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */
2526 #define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */
2527
2528 #define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */
2529 #define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */
2530
2531 #define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */
2532 #define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */
2533
2534 #define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */
2535 #define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */
2536
2537 #define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */
2538 #define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */
2539
2540 #define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */
2541 #define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */
2542
2543 #define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */
2544 #define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */
2545
2546 #define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */
2547 #define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */
2548
2549 #define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */
2550 #define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */
2551
2552 #define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */
2553 #define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */
2554
2555 #define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */
2556 #define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */
2557
2558 #define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */
2559 #define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */
2560
2561 #define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */
2562 #define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */
2563
2564 #define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */
2565 #define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */
2566
2567 #define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */
2568 #define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */
2569
2570 #define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */
2571 #define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */
2572
2573 #define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */
2574 #define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */
2575
2576 #define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */
2577 #define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */
2578
2579 #define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */
2580 #define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */
2581
2582 #define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */
2583 #define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */
2584
2585 #define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */
2586 #define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */
2587
2588 /** \brief PMU Overflow Flag Status Set Register Definitions */
2589 #define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */
2590 #define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */
2591
2592 #define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */
2593 #define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */
2594
2595 #define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */
2596 #define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */
2597
2598 #define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */
2599 #define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */
2600
2601 #define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */
2602 #define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */
2603
2604 #define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */
2605 #define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */
2606
2607 #define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */
2608 #define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */
2609
2610 #define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */
2611 #define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */
2612
2613 #define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */
2614 #define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */
2615
2616 #define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */
2617 #define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */
2618
2619 #define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */
2620 #define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */
2621
2622 #define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */
2623 #define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */
2624
2625 #define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */
2626 #define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */
2627
2628 #define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */
2629 #define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */
2630
2631 #define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */
2632 #define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */
2633
2634 #define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */
2635 #define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */
2636
2637 #define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */
2638 #define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */
2639
2640 #define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */
2641 #define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */
2642
2643 #define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */
2644 #define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */
2645
2646 #define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */
2647 #define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */
2648
2649 #define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */
2650 #define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */
2651
2652 #define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */
2653 #define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */
2654
2655 #define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */
2656 #define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */
2657
2658 #define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */
2659 #define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */
2660
2661 #define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */
2662 #define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */
2663
2664 #define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */
2665 #define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */
2666
2667 #define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */
2668 #define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */
2669
2670 #define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */
2671 #define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */
2672
2673 #define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */
2674 #define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */
2675
2676 #define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */
2677 #define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */
2678
2679 #define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */
2680 #define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */
2681
2682 #define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */
2683 #define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */
2684
2685 /** \brief PMU Overflow Flag Status Clear Register Definitions */
2686 #define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */
2687 #define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */
2688
2689 #define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */
2690 #define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */
2691
2692 #define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */
2693 #define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */
2694
2695 #define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */
2696 #define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */
2697
2698 #define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */
2699 #define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */
2700
2701 #define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */
2702 #define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */
2703
2704 #define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */
2705 #define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */
2706
2707 #define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */
2708 #define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */
2709
2710 #define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */
2711 #define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */
2712
2713 #define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */
2714 #define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */
2715
2716 #define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */
2717 #define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */
2718
2719 #define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */
2720 #define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */
2721
2722 #define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */
2723 #define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */
2724
2725 #define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */
2726 #define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */
2727
2728 #define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */
2729 #define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */
2730
2731 #define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */
2732 #define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */
2733
2734 #define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */
2735 #define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */
2736
2737 #define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */
2738 #define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */
2739
2740 #define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */
2741 #define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */
2742
2743 #define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */
2744 #define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */
2745
2746 #define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */
2747 #define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */
2748
2749 #define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */
2750 #define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */
2751
2752 #define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */
2753 #define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */
2754
2755 #define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */
2756 #define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */
2757
2758 #define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */
2759 #define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */
2760
2761 #define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */
2762 #define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */
2763
2764 #define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */
2765 #define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */
2766
2767 #define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */
2768 #define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */
2769
2770 #define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */
2771 #define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */
2772
2773 #define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */
2774 #define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */
2775
2776 #define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */
2777 #define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */
2778
2779 #define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */
2780 #define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */
2781
2782 /** \brief PMU Software Increment Counter */
2783 #define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */
2784 #define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */
2785
2786 #define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */
2787 #define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */
2788
2789 #define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */
2790 #define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */
2791
2792 #define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */
2793 #define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */
2794
2795 #define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */
2796 #define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */
2797
2798 #define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */
2799 #define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */
2800
2801 #define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */
2802 #define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */
2803
2804 #define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */
2805 #define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */
2806
2807 #define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */
2808 #define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */
2809
2810 #define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */
2811 #define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */
2812
2813 #define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */
2814 #define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */
2815
2816 #define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */
2817 #define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */
2818
2819 #define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */
2820 #define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */
2821
2822 #define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */
2823 #define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */
2824
2825 #define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */
2826 #define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */
2827
2828 #define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */
2829 #define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */
2830
2831 #define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */
2832 #define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */
2833
2834 #define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */
2835 #define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */
2836
2837 #define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */
2838 #define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */
2839
2840 #define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */
2841 #define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */
2842
2843 #define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */
2844 #define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */
2845
2846 #define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */
2847 #define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */
2848
2849 #define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */
2850 #define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */
2851
2852 #define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */
2853 #define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */
2854
2855 #define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */
2856 #define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */
2857
2858 #define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */
2859 #define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */
2860
2861 #define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */
2862 #define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */
2863
2864 #define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */
2865 #define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */
2866
2867 #define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */
2868 #define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */
2869
2870 #define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */
2871 #define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */
2872
2873 #define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */
2874 #define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */
2875
2876 /** \brief PMU Control Register Definitions */
2877 #define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */
2878 #define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */
2879
2880 #define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */
2881 #define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */
2882
2883 #define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */
2884 #define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */
2885
2886 #define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */
2887 #define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */
2888
2889 #define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */
2890 #define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */
2891
2892 #define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */
2893 #define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */
2894
2895 /** \brief PMU Type Register Definitions */
2896 #define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */
2897 #define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */
2898
2899 #define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */
2900 #define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */
2901
2902 #define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */
2903 #define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */
2904
2905 #define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */
2906 #define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */
2907
2908 #define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */
2909 #define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */
2910
2911 /** \brief PMU Authentication Status Register Definitions */
2912 #define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */
2913 #define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */
2914
2915 #define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */
2916 #define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */
2917
2918 #define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */
2919 #define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */
2920
2921 #define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */
2922 #define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */
2923
2924 #define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */
2925 #define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */
2926
2927 #define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */
2928 #define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */
2929
2930 #define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */
2931 #define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */
2932
2933 #define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */
2934 #define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */
2935
2936 /*@} end of group CMSIS_PMU */
2937 #endif
2938
2939
2940 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2941 /**
2942 \ingroup CMSIS_core_register
2943 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
2944 \brief Type definitions for the Memory Protection Unit (MPU)
2945 @{
2946 */
2947
2948 /**
2949 \brief Structure type to access the Memory Protection Unit (MPU).
2950 */
2951 typedef struct
2952 {
2953 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
2954 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
2955 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
2956 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
2957 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
2958 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
2959 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
2960 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
2961 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
2962 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
2963 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
2964 uint32_t RESERVED0[1];
2965 union {
2966 __IOM uint32_t MAIR[2];
2967 struct {
2968 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
2969 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
2970 };
2971 };
2972 } MPU_Type;
2973
2974 #define MPU_TYPE_RALIASES 4U
2975
2976 /** \brief MPU Type Register Definitions */
2977 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
2978 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
2979
2980 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
2981 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
2982
2983 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
2984 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
2985
2986 /** \brief MPU Control Register Definitions */
2987 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
2988 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
2989
2990 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
2991 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
2992
2993 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
2994 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
2995
2996 /** \brief MPU Region Number Register Definitions */
2997 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
2998 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
2999
3000 /** \brief MPU Region Base Address Register Definitions */
3001 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
3002 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
3003
3004 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
3005 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
3006
3007 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
3008 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
3009
3010 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
3011 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
3012
3013 /** \brief MPU Region Limit Address Register Definitions */
3014 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
3015 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
3016
3017 #define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
3018 #define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
3019
3020 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
3021 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
3022
3023 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
3024 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */
3025
3026 /** \brief MPU Memory Attribute Indirection Register 0 Definitions */
3027 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
3028 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
3029
3030 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
3031 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
3032
3033 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
3034 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
3035
3036 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
3037 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
3038
3039 /** \brief MPU Memory Attribute Indirection Register 1 Definitions */
3040 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
3041 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
3042
3043 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
3044 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
3045
3046 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
3047 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
3048
3049 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
3050 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
3051
3052 /*@} end of group CMSIS_MPU */
3053 #endif
3054
3055
3056 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3057 /**
3058 \ingroup CMSIS_core_register
3059 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
3060 \brief Type definitions for the Security Attribution Unit (SAU)
3061 @{
3062 */
3063
3064 /**
3065 \brief Structure type to access the Security Attribution Unit (SAU).
3066 */
3067 typedef struct
3068 {
3069 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
3070 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
3071 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
3072 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
3073 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
3074 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
3075 #else
3076 uint32_t RESERVED0[3];
3077 #endif
3078 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
3079 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
3080 } SAU_Type;
3081
3082 /** \brief SAU Control Register Definitions */
3083 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
3084 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
3085
3086 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
3087 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
3088
3089 /** \brief SAU Type Register Definitions */
3090 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
3091 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
3092
3093 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
3094 /** \brief SAU Region Number Register Definitions */
3095 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
3096 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
3097
3098 /** \brief SAU Region Base Address Register Definitions */
3099 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
3100 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
3101
3102 /** \brief SAU Region Limit Address Register Definitions */
3103 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
3104 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
3105
3106 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
3107 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
3108
3109 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
3110 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
3111
3112 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
3113
3114 /** \brief SAU Secure Fault Status Register Definitions */
3115 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
3116 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
3117
3118 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
3119 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
3120
3121 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
3122 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
3123
3124 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
3125 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
3126
3127 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
3128 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
3129
3130 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
3131 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
3132
3133 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
3134 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
3135
3136 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
3137 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
3138
3139 /*@} end of group CMSIS_SAU */
3140 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3141
3142
3143 /**
3144 \ingroup CMSIS_core_register
3145 \defgroup CMSIS_FPU Floating Point Unit (FPU)
3146 \brief Type definitions for the Floating Point Unit (FPU)
3147 @{
3148 */
3149
3150 /**
3151 \brief Structure type to access the Floating Point Unit (FPU).
3152 */
3153 typedef struct
3154 {
3155 uint32_t RESERVED0[1U];
3156 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
3157 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
3158 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
3159 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
3160 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
3161 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
3162 } FPU_Type;
3163
3164 /** \brief FPU Floating-Point Context Control Register Definitions */
3165 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
3166 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
3167
3168 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
3169 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
3170
3171 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
3172 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
3173
3174 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
3175 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
3176
3177 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
3178 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
3179
3180 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
3181 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
3182
3183 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
3184 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
3185
3186 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
3187 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
3188
3189 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
3190 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
3191
3192 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
3193 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
3194
3195 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
3196 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
3197
3198 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
3199 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
3200
3201 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
3202 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
3203
3204 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
3205 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
3206
3207 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
3208 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
3209
3210 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
3211 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
3212
3213 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
3214 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
3215
3216 /** \brief FPU Floating-Point Context Address Register Definitions */
3217 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
3218 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
3219
3220 /** \brief FPU Floating-Point Default Status Control Register Definitions */
3221 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
3222 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
3223
3224 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
3225 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
3226
3227 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
3228 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
3229
3230 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
3231 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
3232
3233 #define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */
3234 #define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */
3235
3236 #define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */
3237 #define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */
3238
3239 /** \brief FPU Media and VFP Feature Register 0 Definitions */
3240 #define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */
3241 #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */
3242
3243 #define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */
3244 #define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */
3245
3246 #define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */
3247 #define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */
3248
3249 #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */
3250 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */
3251
3252 #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */
3253 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */
3254
3255 #define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */
3256 #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */
3257
3258 /** \brief FPU Media and VFP Feature Register 1 Definitions */
3259 #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */
3260 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */
3261
3262 #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
3263 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */
3264
3265 #define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */
3266 #define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */
3267
3268 #define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */
3269 #define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */
3270
3271 #define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
3272 #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */
3273
3274 #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */
3275 #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
3276
3277 /** \brief FPU Media and VFP Feature Register 2 Definitions */
3278 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
3279 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
3280
3281 /*@} end of group CMSIS_FPU */
3282
3283
3284 /**
3285 \ingroup CMSIS_core_register
3286 \defgroup CMSIS_DCB Debug Control Block
3287 \brief Type definitions for the Debug Control Block Registers
3288 @{
3289 */
3290
3291 /**
3292 \brief Structure type to access the Debug Control Block Registers (DCB).
3293 */
3294 typedef struct
3295 {
3296 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
3297 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
3298 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
3299 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
3300 __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
3301 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
3302 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
3303 } DCB_Type;
3304
3305 /** \brief DCB Debug Halting Control and Status Register Definitions */
3306 #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
3307 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
3308
3309 #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
3310 #define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
3311
3312 #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
3313 #define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
3314
3315 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
3316 #define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
3317
3318 #define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */
3319 #define DCB_DHCSR_S_FPD_Msk (1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */
3320
3321 #define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */
3322 #define DCB_DHCSR_S_SUIDE_Msk (1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */
3323
3324 #define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */
3325 #define DCB_DHCSR_S_NSUIDE_Msk (1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */
3326
3327 #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
3328 #define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
3329
3330 #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
3331 #define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
3332
3333 #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
3334 #define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
3335
3336 #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
3337 #define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
3338
3339 #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
3340 #define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
3341
3342 #define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */
3343 #define DCB_DHCSR_C_PMOV_Msk (1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */
3344
3345 #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
3346 #define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
3347
3348 #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
3349 #define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
3350
3351 #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
3352 #define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
3353
3354 #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
3355 #define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
3356
3357 #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
3358 #define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
3359
3360 /** \brief DCB Debug Core Register Selector Register Definitions */
3361 #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
3362 #define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
3363
3364 #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
3365 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
3366
3367 /** \brief DCB Debug Core Register Data Register Definitions */
3368 #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
3369 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
3370
3371 /** \brief DCB Debug Exception and Monitor Control Register Definitions */
3372 #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
3373 #define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
3374
3375 #define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
3376 #define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
3377
3378 #define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
3379 #define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
3380
3381 #define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
3382 #define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
3383
3384 #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
3385 #define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
3386
3387 #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
3388 #define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
3389
3390 #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
3391 #define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
3392
3393 #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
3394 #define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
3395
3396 #define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
3397 #define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
3398
3399 #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
3400 #define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
3401
3402 #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
3403 #define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
3404
3405 #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
3406 #define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
3407
3408 #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
3409 #define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
3410
3411 #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
3412 #define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
3413
3414 #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
3415 #define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
3416
3417 #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
3418 #define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
3419
3420 #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
3421 #define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
3422
3423 /** \brief DCB Debug Set Clear Exception and Monitor Control Register Definitions */
3424 #define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */
3425 #define DCB_DSCEMCR_CLR_MON_REQ_Msk (1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */
3426
3427 #define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */
3428 #define DCB_DSCEMCR_CLR_MON_PEND_Msk (1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */
3429
3430 #define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */
3431 #define DCB_DSCEMCR_SET_MON_REQ_Msk (1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */
3432
3433 #define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */
3434 #define DCB_DSCEMCR_SET_MON_PEND_Msk (1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */
3435
3436 /** \brief DCB Debug Authentication Control Register Definitions */
3437 #define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */
3438 #define DCB_DAUTHCTRL_UIDEN_Msk (1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */
3439
3440 #define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */
3441 #define DCB_DAUTHCTRL_UIDAPEN_Msk (1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */
3442
3443 #define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */
3444 #define DCB_DAUTHCTRL_FSDMA_Msk (1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */
3445
3446 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
3447 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
3448
3449 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
3450 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
3451
3452 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
3453 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
3454
3455 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
3456 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
3457
3458 /** \brief DCB Debug Security Control and Status Register Definitions */
3459 #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
3460 #define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
3461
3462 #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
3463 #define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
3464
3465 #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
3466 #define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
3467
3468 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
3469 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
3470
3471 /*@} end of group CMSIS_DCB */
3472
3473
3474 /**
3475 \ingroup CMSIS_core_register
3476 \defgroup CMSIS_DIB Debug Identification Block
3477 \brief Type definitions for the Debug Identification Block Registers
3478 @{
3479 */
3480
3481 /**
3482 \brief Structure type to access the Debug Identification Block Registers (DIB).
3483 */
3484 typedef struct
3485 {
3486 uint32_t RESERVED0[2U];
3487 __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
3488 __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
3489 uint32_t RESERVED1[3U];
3490 __IM uint32_t DDEVTYPE; /*!< Offset: 0x01C (R/ ) SCS Device Type Register */
3491 } DIB_Type;
3492
3493 /** \brief DIB Debug Authentication Status Register Definitions */
3494 #define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */
3495 #define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */
3496
3497 #define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */
3498 #define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */
3499
3500 #define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */
3501 #define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */
3502
3503 #define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */
3504 #define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */
3505
3506 #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
3507 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
3508
3509 #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
3510 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
3511
3512 #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
3513 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
3514
3515 #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
3516 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
3517
3518 /** \brief DIB SCS Device Architecture Register Definitions */
3519 #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
3520 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
3521
3522 #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
3523 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
3524
3525 #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
3526 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
3527
3528 #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
3529 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
3530
3531 #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
3532 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
3533
3534 /** \brief DIB SCS Device Type Register Definitions */
3535 #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
3536 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
3537
3538 #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
3539 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
3540
3541 /*@} end of group CMSIS_DIB */
3542
3543
3544 /**
3545 \ingroup CMSIS_core_register
3546 \defgroup CMSIS_core_bitfield Core register bit field macros
3547 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
3548 @{
3549 */
3550
3551 /**
3552 \brief Mask and shift a bit field value for use in a register bit range.
3553 \param[in] field Name of the register bit field.
3554 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
3555 \return Masked and shifted value.
3556 */
3557 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
3558
3559 /**
3560 \brief Mask and shift a register value to extract a bit field value.
3561 \param[in] field Name of the register bit field.
3562 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
3563 \return Masked and shifted bit field value.
3564 */
3565 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
3566
3567 /*@} end of group CMSIS_core_bitfield */
3568
3569
3570 /**
3571 \ingroup CMSIS_core_register
3572 \defgroup CMSIS_core_base Core Definitions
3573 \brief Definitions for base addresses, unions, and structures.
3574 @{
3575 */
3576
3577 /* Memory mapping of Core Hardware */
3578 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
3579 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
3580 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
3581 #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */
3582 #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */
3583 #define DCAR_BASE (0xE001E200UL) /*!< Direct Cache Access Registers */
3584 #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */
3585 #define EWIC_ISA_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller interrupt status access Base Address */
3586 #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */
3587 #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */
3588 #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */
3589 #define EWIC_BASE (0xE0047000UL) /*!< External Wakeup Interrupt Controller Base Address */
3590 #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
3591 #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
3592 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
3593 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
3594 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
3595
3596 #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
3597 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
3598 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
3599 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
3600 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
3601 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
3602 #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */
3603 #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */
3604 #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */
3605 #define DCAR ((DCAR_Type *) DCAR_BASE ) /*!< Direct Read Access to the embedded RAM associated with the L1 instruction and data cache */
3606 #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */
3607 #define EWIC_ISA ((EWIC_ISA_Type *) EWIC_ISA_BASE ) /*!< EWIC interrupt status access struct */
3608 #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */
3609 #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */
3610 #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */
3611 #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
3612 #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
3613
3614 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
3615 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
3616 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
3617 #endif
3618
3619 #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
3620 #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */
3621 #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */
3622 #endif
3623
3624 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3625 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
3626 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
3627 #endif
3628
3629 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
3630 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
3631
3632 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3633 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
3634 #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
3635 #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
3636 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
3637 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
3638 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
3639
3640 #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
3641 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
3642 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
3643 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
3644 #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
3645 #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
3646
3647 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
3648 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
3649 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
3650 #endif
3651
3652 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
3653 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
3654
3655 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3656 /*@} */
3657
3658
3659 /**
3660 \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases
3661 \brief Alias definitions present for backwards compatibility for deprecated symbols.
3662 @{
3663 */
3664
3665 #ifndef CMSIS_DISABLE_DEPRECATED
3666
3667 #define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
3668 #define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk
3669
3670 #endif // CMSIS_DISABLE_DEPRECATED
3671
3672 /*@} */
3673
3674
3675 /*******************************************************************************
3676 * Hardware Abstraction Layer
3677 Core Function Interface contains:
3678 - Core NVIC Functions
3679 - Core SysTick Functions
3680 - Core Debug Functions
3681 - Core Register Access Functions
3682 ******************************************************************************/
3683 /**
3684 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
3685 */
3686
3687
3688
3689 /* ########################## NVIC functions #################################### */
3690 /**
3691 \ingroup CMSIS_Core_FunctionInterface
3692 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
3693 \brief Functions that manage interrupts and exceptions via the NVIC.
3694 @{
3695 */
3696
3697 #ifdef CMSIS_NVIC_VIRTUAL
3698 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
3699 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
3700 #endif
3701 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
3702 #else
3703 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
3704 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
3705 #define NVIC_EnableIRQ __NVIC_EnableIRQ
3706 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
3707 #define NVIC_DisableIRQ __NVIC_DisableIRQ
3708 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
3709 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
3710 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
3711 #define NVIC_GetActive __NVIC_GetActive
3712 #define NVIC_SetPriority __NVIC_SetPriority
3713 #define NVIC_GetPriority __NVIC_GetPriority
3714 #define NVIC_SystemReset __NVIC_SystemReset
3715 #endif /* CMSIS_NVIC_VIRTUAL */
3716
3717 #ifdef CMSIS_VECTAB_VIRTUAL
3718 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
3719 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
3720 #endif
3721 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
3722 #else
3723 #define NVIC_SetVector __NVIC_SetVector
3724 #define NVIC_GetVector __NVIC_GetVector
3725 #endif /* (CMSIS_VECTAB_VIRTUAL) */
3726
3727 #define NVIC_USER_IRQ_OFFSET 16
3728
3729
3730 /* Special LR values for Secure/Non-Secure call handling and exception handling */
3731
3732 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
3733 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
3734
3735 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
3736 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
3737 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
3738 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
3739 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
3740 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
3741 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
3742 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
3743
3744 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
3745 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
3746 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
3747 #else
3748 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
3749 #endif
3750
3751
3752 /**
3753 \brief Set Priority Grouping
3754 \details Sets the priority grouping field using the required unlock sequence.
3755 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
3756 Only values from 0..7 are used.
3757 In case of a conflict between priority grouping and available
3758 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
3759 \param [in] PriorityGroup Priority grouping field.
3760 */
__NVIC_SetPriorityGrouping(uint32_t PriorityGroup)3761 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
3762 {
3763 uint32_t reg_value;
3764 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
3765
3766 reg_value = SCB->AIRCR; /* read old register configuration */
3767 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
3768 reg_value = (reg_value |
3769 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
3770 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
3771 SCB->AIRCR = reg_value;
3772 }
3773
3774
3775 /**
3776 \brief Get Priority Grouping
3777 \details Reads the priority grouping field from the NVIC Interrupt Controller.
3778 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
3779 */
__NVIC_GetPriorityGrouping(void)3780 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
3781 {
3782 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
3783 }
3784
3785
3786 /**
3787 \brief Enable Interrupt
3788 \details Enables a device specific interrupt in the NVIC interrupt controller.
3789 \param [in] IRQn Device specific interrupt number.
3790 \note IRQn must not be negative.
3791 */
__NVIC_EnableIRQ(IRQn_Type IRQn)3792 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
3793 {
3794 if ((int32_t)(IRQn) >= 0)
3795 {
3796 __COMPILER_BARRIER();
3797 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3798 __COMPILER_BARRIER();
3799 }
3800 }
3801
3802
3803 /**
3804 \brief Get Interrupt Enable status
3805 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
3806 \param [in] IRQn Device specific interrupt number.
3807 \return 0 Interrupt is not enabled.
3808 \return 1 Interrupt is enabled.
3809 \note IRQn must not be negative.
3810 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)3811 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
3812 {
3813 if ((int32_t)(IRQn) >= 0)
3814 {
3815 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3816 }
3817 else
3818 {
3819 return(0U);
3820 }
3821 }
3822
3823
3824 /**
3825 \brief Disable Interrupt
3826 \details Disables a device specific interrupt in the NVIC interrupt controller.
3827 \param [in] IRQn Device specific interrupt number.
3828 \note IRQn must not be negative.
3829 */
__NVIC_DisableIRQ(IRQn_Type IRQn)3830 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
3831 {
3832 if ((int32_t)(IRQn) >= 0)
3833 {
3834 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3835 __DSB();
3836 __ISB();
3837 }
3838 }
3839
3840
3841 /**
3842 \brief Get Pending Interrupt
3843 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
3844 \param [in] IRQn Device specific interrupt number.
3845 \return 0 Interrupt status is not pending.
3846 \return 1 Interrupt status is pending.
3847 \note IRQn must not be negative.
3848 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)3849 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
3850 {
3851 if ((int32_t)(IRQn) >= 0)
3852 {
3853 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3854 }
3855 else
3856 {
3857 return(0U);
3858 }
3859 }
3860
3861
3862 /**
3863 \brief Set Pending Interrupt
3864 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
3865 \param [in] IRQn Device specific interrupt number.
3866 \note IRQn must not be negative.
3867 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)3868 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
3869 {
3870 if ((int32_t)(IRQn) >= 0)
3871 {
3872 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3873 }
3874 }
3875
3876
3877 /**
3878 \brief Clear Pending Interrupt
3879 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
3880 \param [in] IRQn Device specific interrupt number.
3881 \note IRQn must not be negative.
3882 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)3883 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
3884 {
3885 if ((int32_t)(IRQn) >= 0)
3886 {
3887 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3888 }
3889 }
3890
3891
3892 /**
3893 \brief Get Active Interrupt
3894 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
3895 \param [in] IRQn Device specific interrupt number.
3896 \return 0 Interrupt status is not active.
3897 \return 1 Interrupt status is active.
3898 \note IRQn must not be negative.
3899 */
__NVIC_GetActive(IRQn_Type IRQn)3900 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
3901 {
3902 if ((int32_t)(IRQn) >= 0)
3903 {
3904 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3905 }
3906 else
3907 {
3908 return(0U);
3909 }
3910 }
3911
3912
3913 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3914 /**
3915 \brief Get Interrupt Target State
3916 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
3917 \param [in] IRQn Device specific interrupt number.
3918 \return 0 if interrupt is assigned to Secure
3919 \return 1 if interrupt is assigned to Non Secure
3920 \note IRQn must not be negative.
3921 */
NVIC_GetTargetState(IRQn_Type IRQn)3922 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
3923 {
3924 if ((int32_t)(IRQn) >= 0)
3925 {
3926 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3927 }
3928 else
3929 {
3930 return(0U);
3931 }
3932 }
3933
3934
3935 /**
3936 \brief Set Interrupt Target State
3937 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
3938 \param [in] IRQn Device specific interrupt number.
3939 \return 0 if interrupt is assigned to Secure
3940 1 if interrupt is assigned to Non Secure
3941 \note IRQn must not be negative.
3942 */
NVIC_SetTargetState(IRQn_Type IRQn)3943 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
3944 {
3945 if ((int32_t)(IRQn) >= 0)
3946 {
3947 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
3948 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3949 }
3950 else
3951 {
3952 return(0U);
3953 }
3954 }
3955
3956
3957 /**
3958 \brief Clear Interrupt Target State
3959 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
3960 \param [in] IRQn Device specific interrupt number.
3961 \return 0 if interrupt is assigned to Secure
3962 1 if interrupt is assigned to Non Secure
3963 \note IRQn must not be negative.
3964 */
NVIC_ClearTargetState(IRQn_Type IRQn)3965 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
3966 {
3967 if ((int32_t)(IRQn) >= 0)
3968 {
3969 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
3970 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3971 }
3972 else
3973 {
3974 return(0U);
3975 }
3976 }
3977 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3978
3979
3980 /**
3981 \brief Set Interrupt Priority
3982 \details Sets the priority of a device specific interrupt or a processor exception.
3983 The interrupt number can be positive to specify a device specific interrupt,
3984 or negative to specify a processor exception.
3985 \param [in] IRQn Interrupt number.
3986 \param [in] priority Priority to set.
3987 \note The priority cannot be set for every processor exception.
3988 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)3989 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
3990 {
3991 if ((int32_t)(IRQn) >= 0)
3992 {
3993 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
3994 }
3995 else
3996 {
3997 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
3998 }
3999 }
4000
4001
4002 /**
4003 \brief Get Interrupt Priority
4004 \details Reads the priority of a device specific interrupt or a processor exception.
4005 The interrupt number can be positive to specify a device specific interrupt,
4006 or negative to specify a processor exception.
4007 \param [in] IRQn Interrupt number.
4008 \return Interrupt Priority.
4009 Value is aligned automatically to the implemented priority bits of the microcontroller.
4010 */
__NVIC_GetPriority(IRQn_Type IRQn)4011 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
4012 {
4013
4014 if ((int32_t)(IRQn) >= 0)
4015 {
4016 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
4017 }
4018 else
4019 {
4020 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
4021 }
4022 }
4023
4024
4025 /**
4026 \brief Encode Priority
4027 \details Encodes the priority for an interrupt with the given priority group,
4028 preemptive priority value, and subpriority value.
4029 In case of a conflict between priority grouping and available
4030 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
4031 \param [in] PriorityGroup Used priority group.
4032 \param [in] PreemptPriority Preemptive priority value (starting from 0).
4033 \param [in] SubPriority Subpriority value (starting from 0).
4034 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
4035 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)4036 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
4037 {
4038 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
4039 uint32_t PreemptPriorityBits;
4040 uint32_t SubPriorityBits;
4041
4042 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
4043 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
4044
4045 return (
4046 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
4047 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
4048 );
4049 }
4050
4051
4052 /**
4053 \brief Decode Priority
4054 \details Decodes an interrupt priority value with a given priority group to
4055 preemptive priority value and subpriority value.
4056 In case of a conflict between priority grouping and available
4057 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
4058 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
4059 \param [in] PriorityGroup Used priority group.
4060 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
4061 \param [out] pSubPriority Subpriority value (starting from 0).
4062 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)4063 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
4064 {
4065 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
4066 uint32_t PreemptPriorityBits;
4067 uint32_t SubPriorityBits;
4068
4069 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
4070 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
4071
4072 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
4073 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
4074 }
4075
4076
4077 /**
4078 \brief Set Interrupt Vector
4079 \details Sets an interrupt vector in SRAM based interrupt vector table.
4080 The interrupt number can be positive to specify a device specific interrupt,
4081 or negative to specify a processor exception.
4082 VTOR must been relocated to SRAM before.
4083 \param [in] IRQn Interrupt number
4084 \param [in] vector Address of interrupt handler function
4085 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)4086 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
4087 {
4088 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
4089 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
4090 __DSB();
4091 }
4092
4093
4094 /**
4095 \brief Get Interrupt Vector
4096 \details Reads an interrupt vector from interrupt vector table.
4097 The interrupt number can be positive to specify a device specific interrupt,
4098 or negative to specify a processor exception.
4099 \param [in] IRQn Interrupt number.
4100 \return Address of interrupt handler function
4101 */
__NVIC_GetVector(IRQn_Type IRQn)4102 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
4103 {
4104 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
4105 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
4106 }
4107
4108
4109 /**
4110 \brief System Reset
4111 \details Initiates a system reset request to reset the MCU.
4112 */
__NVIC_SystemReset(void)4113 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
4114 {
4115 __DSB(); /* Ensure all outstanding memory accesses included
4116 buffered write are completed before reset */
4117 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
4118 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
4119 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
4120 __DSB(); /* Ensure completion of memory access */
4121
4122 for(;;) /* wait until reset */
4123 {
4124 __NOP();
4125 }
4126 }
4127
4128 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
4129 /**
4130 \brief Set Priority Grouping (non-secure)
4131 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
4132 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
4133 Only values from 0..7 are used.
4134 In case of a conflict between priority grouping and available
4135 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
4136 \param [in] PriorityGroup Priority grouping field.
4137 */
TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)4138 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
4139 {
4140 uint32_t reg_value;
4141 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
4142
4143 reg_value = SCB_NS->AIRCR; /* read old register configuration */
4144 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
4145 reg_value = (reg_value |
4146 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
4147 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
4148 SCB_NS->AIRCR = reg_value;
4149 }
4150
4151
4152 /**
4153 \brief Get Priority Grouping (non-secure)
4154 \details Reads the priority grouping field from the non-secure NVIC when in secure state.
4155 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
4156 */
TZ_NVIC_GetPriorityGrouping_NS(void)4157 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
4158 {
4159 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
4160 }
4161
4162
4163 /**
4164 \brief Enable Interrupt (non-secure)
4165 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
4166 \param [in] IRQn Device specific interrupt number.
4167 \note IRQn must not be negative.
4168 */
TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)4169 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
4170 {
4171 if ((int32_t)(IRQn) >= 0)
4172 {
4173 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
4174 }
4175 }
4176
4177
4178 /**
4179 \brief Get Interrupt Enable status (non-secure)
4180 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
4181 \param [in] IRQn Device specific interrupt number.
4182 \return 0 Interrupt is not enabled.
4183 \return 1 Interrupt is enabled.
4184 \note IRQn must not be negative.
4185 */
TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)4186 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
4187 {
4188 if ((int32_t)(IRQn) >= 0)
4189 {
4190 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
4191 }
4192 else
4193 {
4194 return(0U);
4195 }
4196 }
4197
4198
4199 /**
4200 \brief Disable Interrupt (non-secure)
4201 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
4202 \param [in] IRQn Device specific interrupt number.
4203 \note IRQn must not be negative.
4204 */
TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)4205 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
4206 {
4207 if ((int32_t)(IRQn) >= 0)
4208 {
4209 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
4210 }
4211 }
4212
4213
4214 /**
4215 \brief Get Pending Interrupt (non-secure)
4216 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
4217 \param [in] IRQn Device specific interrupt number.
4218 \return 0 Interrupt status is not pending.
4219 \return 1 Interrupt status is pending.
4220 \note IRQn must not be negative.
4221 */
TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)4222 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
4223 {
4224 if ((int32_t)(IRQn) >= 0)
4225 {
4226 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
4227 }
4228 else
4229 {
4230 return(0U);
4231 }
4232 }
4233
4234
4235 /**
4236 \brief Set Pending Interrupt (non-secure)
4237 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
4238 \param [in] IRQn Device specific interrupt number.
4239 \note IRQn must not be negative.
4240 */
TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)4241 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
4242 {
4243 if ((int32_t)(IRQn) >= 0)
4244 {
4245 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
4246 }
4247 }
4248
4249
4250 /**
4251 \brief Clear Pending Interrupt (non-secure)
4252 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
4253 \param [in] IRQn Device specific interrupt number.
4254 \note IRQn must not be negative.
4255 */
TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)4256 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
4257 {
4258 if ((int32_t)(IRQn) >= 0)
4259 {
4260 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
4261 }
4262 }
4263
4264
4265 /**
4266 \brief Get Active Interrupt (non-secure)
4267 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
4268 \param [in] IRQn Device specific interrupt number.
4269 \return 0 Interrupt status is not active.
4270 \return 1 Interrupt status is active.
4271 \note IRQn must not be negative.
4272 */
TZ_NVIC_GetActive_NS(IRQn_Type IRQn)4273 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
4274 {
4275 if ((int32_t)(IRQn) >= 0)
4276 {
4277 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
4278 }
4279 else
4280 {
4281 return(0U);
4282 }
4283 }
4284
4285
4286 /**
4287 \brief Set Interrupt Priority (non-secure)
4288 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
4289 The interrupt number can be positive to specify a device specific interrupt,
4290 or negative to specify a processor exception.
4291 \param [in] IRQn Interrupt number.
4292 \param [in] priority Priority to set.
4293 \note The priority cannot be set for every non-secure processor exception.
4294 */
TZ_NVIC_SetPriority_NS(IRQn_Type IRQn,uint32_t priority)4295 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
4296 {
4297 if ((int32_t)(IRQn) >= 0)
4298 {
4299 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
4300 }
4301 else
4302 {
4303 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
4304 }
4305 }
4306
4307
4308 /**
4309 \brief Get Interrupt Priority (non-secure)
4310 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
4311 The interrupt number can be positive to specify a device specific interrupt,
4312 or negative to specify a processor exception.
4313 \param [in] IRQn Interrupt number.
4314 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
4315 */
TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)4316 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
4317 {
4318
4319 if ((int32_t)(IRQn) >= 0)
4320 {
4321 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
4322 }
4323 else
4324 {
4325 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
4326 }
4327 }
4328 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
4329
4330 /*@} end of CMSIS_Core_NVICFunctions */
4331
4332 /* ########################## MPU functions #################################### */
4333
4334 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
4335
4336 #include "m-profile/armv8m_mpu.h"
4337
4338 #endif
4339
4340 /* ########################## PMU functions and events #################################### */
4341
4342 #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
4343
4344 #include "m-profile/armv8m_pmu.h"
4345
4346 /**
4347 \brief Cortex-M52 PMU events
4348 \note Architectural PMU events can be found in armv8m_pmu.h
4349 */
4350
4351 #define ARMCM52_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */
4352 #define ARMCM52_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */
4353 #define ARMCM52_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */
4354 #define ARMCM52_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */
4355 #define ARMCM52_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */
4356 #define ARMCM52_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */
4357 #define ARMCM52_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */
4358 #define ARMCM52_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */
4359 #define ARMCM52_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */
4360 #define ARMCM52_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */
4361 #define ARMCM52_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */
4362 #define ARMCM52_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */
4363 #define ARMCM52_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */
4364 #define ARMCM52_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */
4365 #define ARMCM52_PMU_AXI_SAHB_WRITE_ACCESS 0xC302 /*!< M-AXI configuration: Any beat access to the M-AXI write interface.M-AHB configuration: Any write beat access to the SYS-AHB interface */
4366 #define ARMCM52_PMU_AXI_SAHB_READ_ACCESS 0xC303 /*!< M-AXI configuration: Any beat access to the M-AXI read interface.M-AHB configuration: Any read beat access to the SYS-AHB interface */
4367 #define ARMCM52_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */
4368 #define ARMCM52_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */
4369 #define ARMCM52_PMU_CDE_INST_RETIRED 0xC402 /*!< CDE instruction architecturally executed. */
4370 #define ARMCM52_PMU_CDE_CX1_INST_RETIRED 0xC404 /*!< CDE CX1 instruction architecturally executed. */
4371 #define ARMCM52_PMU_CDE_CX2_INST_RETIRED 0xC406 /*!< CDE CX2 instruction architecturally executed. */
4372 #define ARMCM52_PMU_CDE_CX3_INST_RETIRED 0xC408 /*!< CDE CX3 instruction architecturally executed. */
4373 #define ARMCM52_PMU_CDE_VCX1_INST_RETIRED 0xC40A /*!< CDE VCX1 instruction architecturally executed. */
4374 #define ARMCM52_PMU_CDE_VCX2_INST_RETIRED 0xC40C /*!< CDE VCX2 instruction architecturally executed. */
4375 #define ARMCM52_PMU_CDE_VCX3_INST_RETIRED 0xC40E /*!< CDE VCX3 instruction architecturally executed. */
4376 #define ARMCM52_PMU_CDE_VCX1_VEC_INST_RETIRED 0xC410 /*!< CDE VCX1 Vector instruction architecturally executed. */
4377 #define ARMCM52_PMU_CDE_VCX2_VEC_INST_RETIRED 0xC412 /*!< CDE VCX2 Vector instruction architecturally executed. */
4378 #define ARMCM52_PMU_CDE_VCX3_VEC_INST_RETIRED 0xC414 /*!< CDE VCX3 Vector instruction architecturally executed. */
4379 #define ARMCM52_PMU_CDE_PRED 0xC416 /*!< Cycles where one or more predicated beats of a CDE instruction architecturally executed. */
4380 #define ARMCM52_PMU_CDE_STALL 0xC417 /*!< Stall cycles caused by a CDE instruction. */
4381 #define ARMCM52_PMU_CDE_STALL_RESOURCE 0xC418 /*!< Stall cycles caused by a CDE instruction because of resource conflicts */
4382 #define ARMCM52_PMU_CDE_STALL_DEPENDENCY 0xC419 /*!< Stall cycles caused by a CDE register dependency. */
4383 #define ARMCM52_PMU_CDE_STALL_CUSTOM 0xC41A /*!< Stall cycles caused by a CDE instruction are generated by the custom hardware. */
4384 #define ARMCM52_PMU_CDE_STALL_OTHER 0xC41B /*!< Stall cycles caused by a CDE instruction are not covered by the other counters. */
4385 #define ARMCM52_PMU_CAHB_WRITE_ACCESS 0xC420 /*!< M-AHB configuration: A Write beat transfer on Code-AHB */
4386 #define ARMCM52_PMU_CAHB_READ_ACCESS 0xC421 /*!< M-AHB configuration: A Read beat transfer on Code-AHB. */
4387
4388 #endif
4389
4390 /* ########################## FPU functions #################################### */
4391 /**
4392 \ingroup CMSIS_Core_FunctionInterface
4393 \defgroup CMSIS_Core_FpuFunctions FPU Functions
4394 \brief Function that provides FPU type.
4395 @{
4396 */
4397
4398 /**
4399 \brief get FPU type
4400 \details returns the FPU type
4401 \returns
4402 - \b 0: No FPU
4403 - \b 1: Single precision FPU
4404 - \b 2: Double + Single precision FPU
4405 */
SCB_GetFPUType(void)4406 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
4407 {
4408 uint32_t mvfr0;
4409
4410 mvfr0 = FPU->MVFR0;
4411 if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
4412 {
4413 return 2U; /* Double + Single precision FPU */
4414 }
4415 else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
4416 {
4417 return 1U; /* Single precision FPU */
4418 }
4419 else
4420 {
4421 return 0U; /* No FPU */
4422 }
4423 }
4424
4425
4426 /*@} end of CMSIS_Core_FpuFunctions */
4427
4428 /* ########################## MVE functions #################################### */
4429 /**
4430 \ingroup CMSIS_Core_FunctionInterface
4431 \defgroup CMSIS_Core_MveFunctions MVE Functions
4432 \brief Function that provides MVE type.
4433 @{
4434 */
4435
4436 /**
4437 \brief get MVE type
4438 \details returns the MVE type
4439 \returns
4440 - \b 0: No Vector Extension (MVE)
4441 - \b 1: Integer Vector Extension (MVE-I)
4442 - \b 2: Floating-point Vector Extension (MVE-F)
4443 */
SCB_GetMVEType(void)4444 __STATIC_INLINE uint32_t SCB_GetMVEType(void)
4445 {
4446 const uint32_t mvfr1 = FPU->MVFR1;
4447 if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos))
4448 {
4449 return 2U;
4450 }
4451 else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos))
4452 {
4453 return 1U;
4454 }
4455 else
4456 {
4457 return 0U;
4458 }
4459 }
4460
4461
4462 /*@} end of CMSIS_Core_MveFunctions */
4463
4464
4465 /* ########################## Cache functions #################################### */
4466
4467 #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
4468 (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
4469 #include "m-profile/armv7m_cachel1.h"
4470 #endif
4471
4472
4473 /* ########################## SAU functions #################################### */
4474 /**
4475 \ingroup CMSIS_Core_FunctionInterface
4476 \defgroup CMSIS_Core_SAUFunctions SAU Functions
4477 \brief Functions that configure the SAU.
4478 @{
4479 */
4480
4481 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
4482
4483 /**
4484 \brief Enable SAU
4485 \details Enables the Security Attribution Unit (SAU).
4486 */
TZ_SAU_Enable(void)4487 __STATIC_INLINE void TZ_SAU_Enable(void)
4488 {
4489 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
4490 }
4491
4492
4493
4494 /**
4495 \brief Disable SAU
4496 \details Disables the Security Attribution Unit (SAU).
4497 */
TZ_SAU_Disable(void)4498 __STATIC_INLINE void TZ_SAU_Disable(void)
4499 {
4500 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
4501 }
4502
4503 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
4504
4505 /*@} end of CMSIS_Core_SAUFunctions */
4506
4507
4508
4509 /* ################### PAC Key functions ########################### */
4510
4511 #if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))
4512 #include "m-profile/armv81m_pac.h"
4513 #endif
4514
4515
4516 /* ################################## Debug Control function ############################################ */
4517 /**
4518 \ingroup CMSIS_Core_FunctionInterface
4519 \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
4520 \brief Functions that access the Debug Control Block.
4521 @{
4522 */
4523
4524
4525 /**
4526 \brief Set Debug Authentication Control Register
4527 \details writes to Debug Authentication Control register.
4528 \param [in] value value to be writen.
4529 */
DCB_SetAuthCtrl(uint32_t value)4530 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
4531 {
4532 __DSB();
4533 __ISB();
4534 DCB->DAUTHCTRL = value;
4535 __DSB();
4536 __ISB();
4537 }
4538
4539
4540 /**
4541 \brief Get Debug Authentication Control Register
4542 \details Reads Debug Authentication Control register.
4543 \return Debug Authentication Control Register.
4544 */
DCB_GetAuthCtrl(void)4545 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
4546 {
4547 return (DCB->DAUTHCTRL);
4548 }
4549
4550
4551 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
4552 /**
4553 \brief Set Debug Authentication Control Register (non-secure)
4554 \details writes to non-secure Debug Authentication Control register when in secure state.
4555 \param [in] value value to be writen
4556 */
TZ_DCB_SetAuthCtrl_NS(uint32_t value)4557 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
4558 {
4559 __DSB();
4560 __ISB();
4561 DCB_NS->DAUTHCTRL = value;
4562 __DSB();
4563 __ISB();
4564 }
4565
4566
4567 /**
4568 \brief Get Debug Authentication Control Register (non-secure)
4569 \details Reads non-secure Debug Authentication Control register when in secure state.
4570 \return Debug Authentication Control Register.
4571 */
TZ_DCB_GetAuthCtrl_NS(void)4572 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
4573 {
4574 return (DCB_NS->DAUTHCTRL);
4575 }
4576 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
4577
4578 /*@} end of CMSIS_Core_DCBFunctions */
4579
4580
4581
4582
4583 /* ################################## Debug Identification function ############################################ */
4584 /**
4585 \ingroup CMSIS_Core_FunctionInterface
4586 \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
4587 \brief Functions that access the Debug Identification Block.
4588 @{
4589 */
4590
4591
4592 /**
4593 \brief Get Debug Authentication Status Register
4594 \details Reads Debug Authentication Status register.
4595 \return Debug Authentication Status Register.
4596 */
DIB_GetAuthStatus(void)4597 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
4598 {
4599 return (DIB->DAUTHSTATUS);
4600 }
4601
4602
4603 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
4604 /**
4605 \brief Get Debug Authentication Status Register (non-secure)
4606 \details Reads non-secure Debug Authentication Status register when in secure state.
4607 \return Debug Authentication Status Register.
4608 */
TZ_DIB_GetAuthStatus_NS(void)4609 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
4610 {
4611 return (DIB_NS->DAUTHSTATUS);
4612 }
4613 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
4614
4615 /*@} end of CMSIS_Core_DCBFunctions */
4616
4617
4618
4619
4620 /* ################################## SysTick function ############################################ */
4621 /**
4622 \ingroup CMSIS_Core_FunctionInterface
4623 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
4624 \brief Functions that configure the System.
4625 @{
4626 */
4627
4628 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
4629
4630 /**
4631 \brief System Tick Configuration
4632 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
4633 Counter is in free running mode to generate periodic interrupts.
4634 \param [in] ticks Number of ticks between two interrupts.
4635 \return 0 Function succeeded.
4636 \return 1 Function failed.
4637 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
4638 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
4639 must contain a vendor-specific implementation of this function.
4640 */
SysTick_Config(uint32_t ticks)4641 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
4642 {
4643 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
4644 {
4645 return (1UL); /* Reload value impossible */
4646 }
4647
4648 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
4649 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
4650 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
4651 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
4652 SysTick_CTRL_TICKINT_Msk |
4653 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
4654 return (0UL); /* Function successful */
4655 }
4656
4657 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
4658 /**
4659 \brief System Tick Configuration (non-secure)
4660 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
4661 Counter is in free running mode to generate periodic interrupts.
4662 \param [in] ticks Number of ticks between two interrupts.
4663 \return 0 Function succeeded.
4664 \return 1 Function failed.
4665 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
4666 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
4667 must contain a vendor-specific implementation of this function.
4668
4669 */
TZ_SysTick_Config_NS(uint32_t ticks)4670 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
4671 {
4672 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
4673 {
4674 return (1UL); /* Reload value impossible */
4675 }
4676
4677 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
4678 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
4679 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
4680 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
4681 SysTick_CTRL_TICKINT_Msk |
4682 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
4683 return (0UL); /* Function successful */
4684 }
4685 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
4686
4687 #endif
4688
4689 /*@} end of CMSIS_Core_SysTickFunctions */
4690
4691
4692
4693 /* ##################################### Debug In/Output function ########################################### */
4694 /**
4695 \ingroup CMSIS_Core_FunctionInterface
4696 \defgroup CMSIS_core_DebugFunctions ITM Functions
4697 \brief Functions that access the ITM debug interface.
4698 @{
4699 */
4700
4701 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
4702 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
4703
4704
4705 /**
4706 \brief ITM Send Character
4707 \details Transmits a character via the ITM channel 0, and
4708 \li Just returns when no debugger is connected that has booked the output.
4709 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
4710 \param [in] ch Character to transmit.
4711 \returns Character to transmit.
4712 */
ITM_SendChar(uint32_t ch)4713 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
4714 {
4715 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
4716 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
4717 {
4718 while (ITM->PORT[0U].u32 == 0UL)
4719 {
4720 __NOP();
4721 }
4722 ITM->PORT[0U].u8 = (uint8_t)ch;
4723 }
4724 return (ch);
4725 }
4726
4727
4728 /**
4729 \brief ITM Receive Character
4730 \details Inputs a character via the external variable \ref ITM_RxBuffer.
4731 \return Received character.
4732 \return -1 No character pending.
4733 */
ITM_ReceiveChar(void)4734 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
4735 {
4736 int32_t ch = -1; /* no character available */
4737
4738 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
4739 {
4740 ch = ITM_RxBuffer;
4741 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
4742 }
4743
4744 return (ch);
4745 }
4746
4747
4748 /**
4749 \brief ITM Check Character
4750 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
4751 \return 0 No character available.
4752 \return 1 Character available.
4753 */
ITM_CheckChar(void)4754 __STATIC_INLINE int32_t ITM_CheckChar (void)
4755 {
4756
4757 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
4758 {
4759 return (0); /* no character available */
4760 }
4761 else
4762 {
4763 return (1); /* character available */
4764 }
4765 }
4766
4767 /*@} end of CMSIS_core_DebugFunctions */
4768
4769
4770
4771
4772 #ifdef __cplusplus
4773 }
4774 #endif
4775
4776 #endif /* __CORE_CM52_H_DEPENDANT */
4777
4778 #endif /* __CMSIS_GENERIC */
4779
4780
4781
4782
4783
4784
