Searched refs:PrivilegedArchitecture (Results 1 – 11 of 11) sorted by relevance
| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Cores/RiscV/ |
| D | Ri5cy.cs | 15 … 0, [NameAlias("privilegeArchitecture")] PrivilegedArchitecture privilegedArchitecture = Privilege… in Ri5cy()
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| D | IbexRiscV32.cs | 15 … 0, [NameAlias("privilegeArchitecture")] PrivilegedArchitecture privilegedArchitecture = Privilege… in IbexRiscV32()
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| D | RiscV32.cs | 21 …[NameAlias("privilegeArchitecture")] PrivilegedArchitecture privilegedArchitecture = PrivilegedArc… in RiscV32()
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| D | RiscV64.cs | 21 …[NameAlias("privilegeArchitecture")] PrivilegedArchitecture privilegedArchitecture = PrivilegedArc… in RiscV64()
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| D | VeeR_EL2.cs | 18 …er timeProvider = null, uint hartId = 0, PrivilegedArchitecture privilegedArchitecture = Privilege… in VeeR_EL2()
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| D | VexRiscv.cs | 20 …ll, [NameAlias("privilegeArchitecture")] PrivilegedArchitecture privilegedArchitecture = Privilege… in VexRiscv()
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| D | Minerva.cs | 17 …eProvider = null) : base(machine, "rv32i", timeProvider, hartId, PrivilegedArchitecture.Priv1_09, … in Minerva()
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| D | BaseRiscV.cs | 35 PrivilegedArchitecture privilegedArchitecture, in BaseRiscV()
187 …if(privilegedArchitecture >= PrivilegedArchitecture.Priv1_10 && IsValidInterruptOnlyInV1_09(number… in OnGPIO()
859 private readonly PrivilegedArchitecture privilegedArchitecture;
1002 public enum PrivilegedArchitecture enum in Antmicro.Renode.Peripherals.CPU.BaseRiscV
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| D | PicoRV32.cs | 20 …esetVectorAddress = 0x10) : base(machine, cpuType, null, hartId, PrivilegedArchitecture.Priv1_09, … in PicoRV32()
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| D | CV32E40P.cs | 17 … 0, [NameAlias("privilegeArchitecture")] PrivilegedArchitecture privilegedArchitecture = Privilege… in CV32E40P()
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| D | OpenTitan_BigNumberAcceleratorCore.cs | 27 …rv32im_zicsr", machine: null, hartId: 0, privilegedArchitecture: PrivilegedArchitecture.Priv1_10, … in OpenTitan_BigNumberAcceleratorCore()
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