1 // 2 // Copyright (c) 2010-2024 Antmicro 3 // 4 // This file is licensed under the MIT License. 5 // Full license text is available in 'licenses/MIT.txt'. 6 // 7 using Antmicro.Renode.Core; 8 using Antmicro.Renode.Peripherals.Timers; 9 using Endianess = ELFSharp.ELF.Endianess; 10 11 namespace Antmicro.Renode.Peripherals.CPU 12 { 13 public partial class Ri5cy : RiscV32 14 { Ri5cy(IMachine machine, IRiscVTimeProvider timeProvider = null, uint hartId = 0, [NameAlias(R)] PrivilegedArchitecture privilegedArchitecture = PrivilegedArchitecture.Priv1_10, Endianess endianness = Endianess.LittleEndian, string cpuType = R)15 public Ri5cy(IMachine machine, IRiscVTimeProvider timeProvider = null, uint hartId = 0, [NameAlias("privilegeArchitecture")] PrivilegedArchitecture privilegedArchitecture = PrivilegedArchitecture.Priv1_10, Endianess endianness = Endianess.LittleEndian, string cpuType = "rv32imc_zicsr_zifencei") : base(machine, cpuType, timeProvider, hartId, privilegedArchitecture, endianness) 16 { 17 // enable all interrupt sources 18 MIE = 0xffffffff; 19 20 CSRValidation = CSRValidationLevel.None; 21 22 // register custom CSRs 23 // TODO: add support for HW loops 24 RegisterCSR((ulong)0x7b0, () => 0u, _ => {}); //lpstart0 25 RegisterCSR((ulong)0x7b1, () => 0u, _ => {}); //lpend1 26 RegisterCSR((ulong)0x7b2, () => 0u, _ => {}); //lpcount0 27 28 RegisterCSR((ulong)0x7b4, () => 0u, _ => {}); //lpstart1 29 RegisterCSR((ulong)0x7b5, () => 0u, _ => {}); //lpend1 30 RegisterCSR((ulong)0x7b6, () => 0u, _ => {}); //lpcount1 31 } 32 } 33 } 34 35
