1 // 2 // Copyright (c) 2010-2024 Antmicro 3 // 4 // This file is licensed under the MIT License. 5 // Full license text is available in 'licenses/MIT.txt'. 6 // 7 using System; 8 using Antmicro.Renode.Core; 9 using Antmicro.Renode.Logging; 10 using Antmicro.Renode.Peripherals.Timers; 11 using Antmicro.Renode.Utilities; 12 using Endianess = ELFSharp.ELF.Endianess; 13 14 namespace Antmicro.Renode.Peripherals.CPU 15 { 16 public class VeeR_EL2 : RiscV32 17 { VeeR_EL2(IMachine machine, IRiscVTimeProvider timeProvider = null, uint hartId = 0, PrivilegedArchitecture privilegedArchitecture = PrivilegedArchitecture.Priv1_12, Endianess endianness = Endianess.LittleEndian, string cpuType = R, PrivilegeLevels privilegeLevels = PrivilegeLevels.MachineUser)18 public VeeR_EL2(IMachine machine, IRiscVTimeProvider timeProvider = null, uint hartId = 0, PrivilegedArchitecture privilegedArchitecture = PrivilegedArchitecture.Priv1_12, 19 Endianess endianness = Endianess.LittleEndian, string cpuType = "rv32imc_zicsr_zifencei_zba_zbb_zbc_zbs", PrivilegeLevels privilegeLevels = PrivilegeLevels.MachineUser) 20 : base(machine, cpuType, timeProvider, hartId, privilegedArchitecture, endianness, allowUnalignedAccesses: true, privilegeLevels: privilegeLevels, pmpNumberOfAddrBits: 30) 21 { 22 RegisterCustomCSRs(); 23 } 24 RegisterCustomCSRs()25 private void RegisterCustomCSRs() 26 { 27 CreateCSRStub(CustomCSR.RegionAccessControl, "mrac"); 28 CreateCSRStub(CustomCSR.CorePauseControl, "mcpc"); 29 CreateCSRStub(CustomCSR.MemorySynchronizationTrigger, "dmst"); 30 CreateCSRStub(CustomCSR.PowerManagementControl, "mpmc"); 31 CreateCSRStub(CustomCSR.ICacheArrayWayIndexSelection, "dicawics"); 32 CreateCSRStub(CustomCSR.ICacheArrayData0, "dicad0"); 33 CreateCSRStub(CustomCSR.ICacheArrayData1, "dicad1"); 34 CreateCSRStub(CustomCSR.ICacheArrayGo, "dicago"); 35 CreateCSRStub(CustomCSR.ICacheDataArray0High, "dicac0h"); 36 CreateCSRStub(CustomCSR.ForceDebugHaltThreshold, "mfdht"); 37 CreateCSRStub(CustomCSR.ForceDebugHaltStatus, "mfdhs"); 38 CreateCSRStub(CustomCSR.InternalTimerCounter0, "mitcnt0"); 39 CreateCSRStub(CustomCSR.InternalTimerBound0, "mitb0"); 40 CreateCSRStub(CustomCSR.InternalTimerControl0, "mitctl0"); 41 CreateCSRStub(CustomCSR.InternalTimerCounter1, "mitcnt1"); 42 CreateCSRStub(CustomCSR.InternalTimerBound1, "mitb1"); 43 CreateCSRStub(CustomCSR.InternalTimerControl1, "mitctl1"); 44 CreateCSRStub(CustomCSR.ICacheErrorCounterThreshold, "micect"); 45 CreateCSRStub(CustomCSR.ICCMCorrectableErrorCounterThreshold, "miccmect"); 46 CreateCSRStub(CustomCSR.DCCMCorrectableErrorCounterThreshold, "mdccmect"); 47 CreateCSRStub(CustomCSR.ClockGatingControl, "mcgc"); 48 CreateCSRStub(CustomCSR.FeatureDisableControl, "mfdc"); 49 CreateCSRStub(CustomCSR.MachineSecondaryCause, "mscause"); 50 CreateCSRStub(CustomCSR.DBUSErrorAddressUnlock, "mdeau"); 51 CreateCSRStub(CustomCSR.ExternalInterruptVectorTable, "meivt"); 52 CreateCSRStub(CustomCSR.ExternalInterruptPriorityThreshold, "meipt"); 53 CreateCSRStub(CustomCSR.ExternalInterruptClaimIDPriorityLevelCaptureTrigger, "meicpct"); 54 CreateCSRStub(CustomCSR.ExternalInterruptClaimIDPriorityLevel, "meicidpl"); 55 CreateCSRStub(CustomCSR.ExternalInterruptCurrentPriorityLevel, "meicurpl"); 56 CreateCSRStub(CustomCSR.DBUSFirstErrorAddressCapture, "mdseac"); 57 CreateCSRStub(CustomCSR.ExternalInterruptHandlerAddressPointer, "meihap"); 58 } 59 CreateCSRStub(IConvertible csr, string name, ulong returnValue = 0)60 private void CreateCSRStub(IConvertible csr, string name, ulong returnValue = 0) 61 { 62 var offset = Convert.ToUInt64(csr); 63 RegisterCSR(Convert.ToUInt64(csr), 64 readOperation: () => 65 { 66 this.WarningLog("Reading 0x{0:X} from an unimplemented CSR: {1} (0x{2:X})", returnValue, name, offset); 67 return returnValue; 68 }, 69 writeOperation: value => 70 { 71 this.WarningLog("Writing 0x{0:X} to unimplemnted CSR: {1} (0x{2:X})", value, name, offset); 72 }); 73 } 74 75 private enum CustomCSR : ulong 76 { 77 RegionAccessControl = 0x7C0, // mrac 78 CorePauseControl = 0x7C2, // mcpc 79 MemorySynchronizationTrigger = 0x7C4, // dmst 80 PowerManagementControl = 0x7C6, // mpmc 81 ICacheArrayWayIndexSelection = 0x7C8, // dicawics 82 ICacheArrayData0 = 0x7C9, // dicad0 83 ICacheArrayData1 = 0x7CA, // dicad1 84 ICacheArrayGo = 0x7CB, // dicago 85 ICacheDataArray0High = 0x7CC, // dicac0h 86 ForceDebugHaltThreshold = 0x7CE, // mfdht 87 ForceDebugHaltStatus = 0x7CF, // mfdhs 88 InternalTimerCounter0 = 0x7D2, // mitcnt0 89 InternalTimerBound0 = 0x7D3, // mitb0 90 InternalTimerControl0 = 0x7D4, // mitctl0 91 InternalTimerCounter1 = 0x7D5, // mitcnt1 92 InternalTimerBound1 = 0x7D6, // mitb1 93 InternalTimerControl1 = 0x7D7, // mitctl1 94 ICacheErrorCounterThreshold = 0x7F0, // micect 95 ICCMCorrectableErrorCounterThreshold = 0x7F1, // miccmect 96 DCCMCorrectableErrorCounterThreshold = 0x7F2, // mdccmect 97 ClockGatingControl = 0x7F8, // mcgc 98 FeatureDisableControl = 0x7F9, // mfdc 99 MachineSecondaryCause = 0x7FF, // mscause 100 DBUSErrorAddressUnlock = 0xBC0, // mdeau 101 ExternalInterruptVectorTable = 0xBC8, // meivt 102 ExternalInterruptPriorityThreshold = 0xBC9, // meipt 103 ExternalInterruptClaimIDPriorityLevelCaptureTrigger = 0xBCA, // meicpct 104 ExternalInterruptClaimIDPriorityLevel = 0xBCB, // meicidpl 105 ExternalInterruptCurrentPriorityLevel = 0xBCC, // meicurpl 106 DBUSFirstErrorAddressCapture = 0xFC0, // mdseac 107 ExternalInterruptHandlerAddressPointer = 0xFC8, // meihap 108 } 109 } 110 } 111
