1 //
2 // Copyright (c) 2010-2024 Antmicro
3 //
4 // This file is licensed under the MIT License.
5 // Full license text is available in 'licenses/MIT.txt'.
6 //
7 using Antmicro.Renode.Core;
8 using Antmicro.Renode.Peripherals.Timers;
9 using Endianess = ELFSharp.ELF.Endianess;
10 
11 namespace Antmicro.Renode.Peripherals.CPU
12 {
13     public partial class IbexRiscV32 : RiscV32
14     {
IbexRiscV32(IMachine machine, IRiscVTimeProvider timeProvider = null, uint hartId = 0, [NameAlias(R)] PrivilegedArchitecture privilegedArchitecture = PrivilegedArchitecture.Priv1_11, Endianess endianness = Endianess.LittleEndian, string cpuType = R, bool allowUnalignedAccesses = true, ulong? nmiVectorAddress = null, uint? nmiVectorLength = null)15         public IbexRiscV32(IMachine machine, IRiscVTimeProvider timeProvider = null, uint hartId = 0, [NameAlias("privilegeArchitecture")] PrivilegedArchitecture privilegedArchitecture = PrivilegedArchitecture.Priv1_11, Endianess endianness = Endianess.LittleEndian, string cpuType = "rv32imcu_zicsr_zifencei", bool allowUnalignedAccesses = true, ulong? nmiVectorAddress = null, uint? nmiVectorLength = null) : base(machine, cpuType, timeProvider, hartId, privilegedArchitecture, endianness, allowUnalignedAccesses: allowUnalignedAccesses, interruptMode: InterruptMode.Vectored, nmiVectorAddress: nmiVectorAddress, nmiVectorLength: nmiVectorLength)
16         {
17             RegisterCustomCSRs();
18         }
19 
RegisterCustomCSRs()20         private void RegisterCustomCSRs()
21         {
22             RegisterCSR((ulong)CSRs.CpuControl, () => 0ul, _ => {});
23         }
24 
25         private enum CSRs
26         {
27             CpuControl = 0x7c0,
28         }
29     }
30 }
31