Searched defs:hartId (Results 1 – 12 of 12) sorted by relevance
| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Cores/RiscV/ |
| D | Ri5cy.cs | 15 …public Ri5cy(IMachine machine, IRiscVTimeProvider timeProvider = null, uint hartId = 0, [NameAlias… in Ri5cy()
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| D | IbexRiscV32.cs | 15 …public IbexRiscV32(IMachine machine, IRiscVTimeProvider timeProvider = null, uint hartId = 0, [Nam… in IbexRiscV32()
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| D | Minerva.cs | 17 …public Minerva(IMachine machine, uint hartId = 0, IRiscVTimeProvider timeProvider = null) : base(m… in Minerva()
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| D | RiscV32.cs | 20 uint hartId = 0, in RiscV32()
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| D | RiscV64.cs | 20 uint hartId = 0, in RiscV64()
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| D | OpenTitan_PlatformLevelInterruptController.cs | 110 …twareInterruptRegister(Dictionary<long, DoubleWordRegister> registersMap, long offset, uint hartId) in AddContextSoftwareInterruptRegister()
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| D | VexRiscv.cs | 20 …public VexRiscv(IMachine machine, uint hartId = 0, IRiscVTimeProvider timeProvider = null, [NameAl… in VexRiscv()
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| D | VeeR_EL2.cs | 18 …public VeeR_EL2(IMachine machine, IRiscVTimeProvider timeProvider = null, uint hartId = 0, Privile… in VeeR_EL2()
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| D | PicoRV32.cs | 20 …public PicoRV32(IMachine machine, string cpuType, bool latchedIrqs = true, uint hartId = 0, uint r… in PicoRV32()
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| D | CV32E40P.cs | 17 …public CV32E40P(IMachine machine, IRiscVTimeProvider timeProvider = null, uint hartId = 0, [NameAl… in CV32E40P()
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| D | BaseRiscV.cs | 32 uint hartId, in BaseRiscV()
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| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Cores/RiscV/PLIC/ |
| D | PlatformLevelInterruptControllerBase.cs | 178 …orityThresholdRegister(Dictionary<long, DoubleWordRegister> registersMap, long offset, uint hartId) in AddContextPriorityThresholdRegister()
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