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/Linux-v6.1/Documentation/devicetree/bindings/net/
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
22 SGMII The DP83869HM supports Media Conversion in Managed mode. In this mode,
[all …]
Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
[all …]
Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-controller.yaml#"
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
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Dsff,sfp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
11 - Russell King <linux@armlinux.org.uk>
16 - sff,sfp # for SFP modules
17 - sff,sff # for soldered down SFF modules
19 i2c-bus:
24 maximum-power-milliwatt:
28 allowable by a module in the slot, in milli-Watts. Presently, modules can
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/Linux-v6.1/Documentation/devicetree/bindings/net/can/
Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
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/Linux-v6.1/drivers/net/hamradio/
Dz8530.h1 /* SPDX-License-Identifier: GPL-2.0 */
34 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
40 #define TxINT_ENAB 0x2 /* Tx Int Enable */
58 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
60 #define ENT_HM 0x10 /* Enter Hunt Mode */
79 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
80 #define EXTSYNC 0x30 /* External Sync Mode */
82 #define X1CLK 0x0 /* x1 clock mode */
83 #define X16CLK 0x40 /* x16 clock mode */
84 #define X32CLK 0x80 /* x32 clock mode */
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/Linux-v6.1/tools/spi/
Dspidev_test.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
39 static uint32_t mode; variable
71 while (length-- > 0) { in hex_dump()
91 * Unescape - process hexadecimal escape character
92 * converts shell input "\x23" -> 0x23
118 static void transfer(int fd, uint8_t const *tx, uint8_t const *rx, size_t len) in transfer() argument
123 .tx_buf = (unsigned long)tx, in transfer()
131 if (mode & SPI_TX_OCTAL) in transfer()
133 else if (mode & SPI_TX_QUAD) in transfer()
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/Linux-v6.1/arch/arm64/boot/dts/microchip/
Dsparx5_pcb134_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
17 compatible = "gpio-leds";
53 default-state = "off";
58 default-state = "off";
63 default-state = "off";
68 default-state = "off";
73 default-state = "off";
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Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
17 compatible = "gpio-leds";
21 default-state = "off";
26 default-state = "off";
31 default-state = "off";
36 default-state = "off";
41 default-state = "off";
[all …]
/Linux-v6.1/drivers/tty/serial/
Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
29 int tx_stopped; /* Output is suspended. */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
87 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
92 #define TxINT_ENAB 0x2 /* Tx Int Enable */
110 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
112 #define ENT_HM 0x10 /* Enter Hunt Mode */
132 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
[all …]
Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
66 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
72 #define TxINT_ENAB 0x2 /* Tx Int Enable */
91 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
93 #define ENT_HM 0x10 /* Enter Hunt Mode */
113 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
114 #define EXTSYNC 0x30 /* External Sync Mode */
116 #define X1CLK 0x0 /* x1 clock mode */
117 #define X16CLK 0x40 /* x16 clock mode */
[all …]
Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
58 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
64 #define TxINT_ENAB 0x2 /* Tx Int Enable */
83 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
85 #define ENT_HM 0x10 /* Enter Hunt Mode */
105 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
106 #define EXTSYNC 0x30 /* External Sync Mode */
108 #define X1CLK 0x0 /* x1 clock mode */
109 #define X16CLK 0x40 /* x16 clock mode */
[all …]
Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
[all …]
/Linux-v6.1/drivers/net/ethernet/sun/
Dsungem.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 #define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
45 #define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */
46 #define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */
47 #define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */
52 #define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
96 * This register is used to perform a global reset of the RX and TX portions
97 * of the GEM asic. Setting the RX or TX reset bit will start the reset.
[all …]
/Linux-v6.1/arch/m68k/include/asm/
Dmcfuart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfuart.h -- ColdFire internal UART support defines.
7 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
29 #define MCFUART_UMR 0x00 /* Mode register (r/w) */
52 #define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
53 #define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
57 * Define bit flags in Mode Register 1 (MR1).
62 #define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
63 #define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
77 * Define bit flags in Mode Register 2 (MR2).
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/Linux-v6.1/sound/drivers/mpu401/
Dmpu401_uart.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Routines for control of MPU-401 in UART mode
6 * MPU-401 supports UART mode which is not capable generate transmit
7 * interrupts thus output is done via polling. Without interrupt,
10 * 13-03-2003:
12 * are port and mmio. For other kind of I/O, set mpu->read and
13 * mpu->write to your own I/O functions.
28 MODULE_DESCRIPTION("Routines for control of MPU-401 in UART mode");
39 (!(mpu->read(mpu, MPU401C(mpu)) & MPU401_RX_EMPTY))
41 (!(mpu->read(mpu, MPU401C(mpu)) & MPU401_TX_FULL))
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/Linux-v6.1/drivers/staging/rtl8192u/
Dr819xU_cmdpkt.c1 // SPDX-License-Identifier: GPL-2.0
7 * (RTL8190 TX/RX command packet handler Source C File)
9 * Note: The module is responsible for handling TX and RX command packet.
10 * 1. TX : Send set and query configuration command packet.
11 * 2. RX : Receive tx feedback, beacon state, query configuration
42 memcpy((unsigned char *)(skb->cb), &dev, sizeof(dev)); in SendTxCommandPacket()
43 tcb_desc = (struct cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); in SendTxCommandPacket()
44 tcb_desc->queue_index = TXCMD_QUEUE; in SendTxCommandPacket()
45 tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_NORMAL; in SendTxCommandPacket()
46 tcb_desc->bLastIniPkt = 0; in SendTxCommandPacket()
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/Linux-v6.1/samples/pktgen/
Dparameters.sh2 # SPDX-License-Identifier: GPL-2.0
8 echo "Usage: $0 [-vx] -i ethX"
9 echo " -i : (\$DEV) output interface/device (required)"
10 echo " -s : (\$PKT_SIZE) packet size"
11 echo " -d : (\$DEST_IP) destination IP. CIDR (e.g. 198.18.0.0/15) is also allowed"
12 echo " -m : (\$DST_MAC) destination MAC-addr"
13 echo " -p : (\$DST_PORT) destination PORT range (e.g. 433-444) is also allowed"
14 echo " -k : (\$UDP_CSUM) enable UDP tx checksum"
15 echo " -t : (\$THREADS) threads to start"
16 echo " -f : (\$F_THREAD) index of first thread (zero indexed CPU number)"
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/Linux-v6.1/Documentation/devicetree/bindings/sound/
Dfsl,sai.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
21 - enum:
22 - fsl,vf610-sai
23 - fsl,imx6sx-sai
24 - fsl,imx6ul-sai
25 - fsl,imx7ulp-sai
26 - fsl,imx8mq-sai
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/Linux-v6.1/Documentation/userspace-api/media/cec/
Dcec-pin-error-inj.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
7 has low-level support for the CEC bus. Most hardware today will have
8 high-level CEC support where the hardware deals with driving the CEC bus,
17 Currently only the cec-gpio driver (when the CEC line is directly
18 connected to a pull-up GPIO line) and the AllWinner A10/A20 drm driver
23 now an ``error-inj`` file.
30 With ``cat error-inj`` you can see both the possible commands and the current
33 $ cat /sys/kernel/debug/cec/cec0/error-inj
35 # clear clear all rx and tx error injections
36 # rx-clear clear all rx error injections
[all …]
/Linux-v6.1/Documentation/networking/device_drivers/ethernet/3com/
Dvortex.rst1 .. SPDX-License-Identifier: GPL-2.0
20 - Andrew Morton
21 - Netdev mailing list <netdev@vger.kernel.org>
22 - Linux kernel mailing list <linux-kernel@vger.kernel.org>
28 Since kernel 2.3.99-pre6, this driver incorporates the support for the
29 3c575-series Cardbus cards which used to be handled by 3c575_cb.c.
33 - 3c590 Vortex 10Mbps
34 - 3c592 EISA 10Mbps Demon/Vortex
35 - 3c597 EISA Fast Demon/Vortex
36 - 3c595 Vortex 100baseTx
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/Linux-v6.1/drivers/net/phy/
Ddp83867.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/nvmem-consumer.h>
19 #include <dt-bindings/net/ti-dp83867.h>
185 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
192 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
197 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
198 mac = (const u8 *)ndev->dev_addr; in dp83867_set_wol()
201 return -EINVAL; in dp83867_set_wol()
215 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol()
217 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83867_set_wol()
[all …]
/Linux-v6.1/drivers/spi/
Dspi-rspi.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on spi-sh.c:
21 #include <linux/dma-mapping.h>
41 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
69 /* SPCR - Control Register */
74 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
75 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
77 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
78 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
79 /* QSPI on R-Car Gen2 only */
[all …]
/Linux-v6.1/drivers/staging/r8188eu/include/
DHal8188EPhyCfg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
29 u32 rfintfo; /* output data: */
31 u32 rfintfe; /* output enable: */
37 u32 rfTxGainStage; /* Tx gain stage: */
45 u32 rfSwitchControl; /* Tx Rx antenna control : */
60 u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */
63 u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */
66 u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */
68 u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for
[all …]
/Linux-v6.1/drivers/net/ethernet/brocade/bna/
Dbna.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Linux network driver for QLogic BR-series Converged Network Adapter.
6 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
7 * Copyright (c) 2014-2015 QLogic Corporation
26 * input : _addr-> os dma addr in host endian format,
27 * output : _bna_dma_addr-> pointer to hw dma addr
33 (_bna_dma_addr)->msb = ((struct bna_dma_addr *)&tmp_addr)->msb; \
34 (_bna_dma_addr)->lsb = ((struct bna_dma_addr *)&tmp_addr)->lsb; \
38 * input : _bna_dma_addr-> pointer to hw dma addr
39 * output : _addr-> os dma addr in host endian format
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