Lines Matching +full:tx +full:- +full:output +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
8 * Based on spi-sh.c:
21 #include <linux/dma-mapping.h>
41 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
69 /* SPCR - Control Register */
74 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
75 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
77 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
78 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
79 /* QSPI on R-Car Gen2 only */
80 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
81 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
83 /* SSLP - Slave Select Polarity Register */
86 /* SPPCR - Pin Control Register */
90 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
91 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
93 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
94 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
96 /* SPSR - Status Register */
101 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */
105 /* SPSCR - Sequence Control Register */
108 /* SPSSR - Sequence Status Register */
112 /* SPDCR - Data Control Register */
123 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
126 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
128 /* SPCKD - Clock Delay Register */
129 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
131 /* SSLND - Slave Select Negation Delay Register */
132 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
134 /* SPND - Next-Access Delay Register */
135 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
137 /* SPCR2 - Control Register 2 */
138 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
143 /* SPCMDn - Command Registers */
146 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
149 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
156 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
169 /* SPBFCR - Buffer Control Register */
174 /* QSPI on R-Car Gen2 */
188 spinlock_t lock; /* Protects RMW-access to RSPI_SSLP */
202 iowrite8(data, rspi->addr + offset); in rspi_write8()
207 iowrite16(data, rspi->addr + offset); in rspi_write16()
212 iowrite32(data, rspi->addr + offset); in rspi_write32()
217 return ioread8(rspi->addr + offset); in rspi_read8()
222 return ioread16(rspi->addr + offset); in rspi_read16()
227 if (rspi->byte_access) in rspi_write_data()
235 if (rspi->byte_access) in rspi_read_data()
259 clksrc = clk_get_rate(rspi->clk); in rspi_set_rate()
260 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1; in rspi_set_rate()
263 spbr = DIV_ROUND_UP(spbr + 1, 2) - 1; in rspi_set_rate()
267 rspi->spcmd |= SPCMD_BRDV(brdv); in rspi_set_rate()
268 rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * (spbr + 1)); in rspi_set_rate()
276 /* Sets output mode, MOSI signal, and (optionally) loopback */ in rspi_set_config_register()
277 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); in rspi_set_config_register()
282 /* Disable dummy transmission, set 16-bit word access, 1 frame */ in rspi_set_config_register()
284 rspi->byte_access = 0; in rspi_set_config_register()
286 /* Sets RSPCK, SSL, next-access delay value */ in rspi_set_config_register()
296 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); in rspi_set_config_register()
297 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); in rspi_set_config_register()
299 /* Sets RSPI mode */ in rspi_set_config_register()
310 /* Sets output mode, MOSI signal, and (optionally) loopback */ in rspi_rz_set_config_register()
311 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); in rspi_rz_set_config_register()
318 rspi->byte_access = 1; in rspi_rz_set_config_register()
320 /* Sets RSPCK, SSL, next-access delay value */ in rspi_rz_set_config_register()
327 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); in rspi_rz_set_config_register()
328 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); in rspi_rz_set_config_register()
330 /* Sets RSPI mode */ in rspi_rz_set_config_register()
344 /* Sets output mode, MOSI signal, and (optionally) loopback */ in qspi_set_config_register()
345 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); in qspi_set_config_register()
348 clksrc = clk_get_rate(rspi->clk); in qspi_set_config_register()
349 if (rspi->speed_hz >= clksrc) { in qspi_set_config_register()
351 rspi->speed_hz = clksrc; in qspi_set_config_register()
353 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz); in qspi_set_config_register()
359 rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * spbr); in qspi_set_config_register()
362 rspi->spcmd |= SPCMD_BRDV(brdv); in qspi_set_config_register()
366 rspi->byte_access = 1; in qspi_set_config_register()
368 /* Sets RSPCK, SSL, next-access delay value */ in qspi_set_config_register()
375 rspi->spcmd |= SPCMD_SPB_8BIT; in qspi_set_config_register()
377 rspi->spcmd |= SPCMD_SPB_16BIT; in qspi_set_config_register()
379 rspi->spcmd |= SPCMD_SPB_32BIT; in qspi_set_config_register()
381 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN; in qspi_set_config_register()
393 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); in qspi_set_config_register()
395 /* Sets RSPI mode */ in qspi_set_config_register()
464 rspi->spsr = rspi_read8(rspi, RSPI_SPSR); in rspi_wait_for_interrupt()
465 if (rspi->spsr & wait_mask) in rspi_wait_for_interrupt()
469 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); in rspi_wait_for_interrupt()
470 if (ret == 0 && !(rspi->spsr & wait_mask)) in rspi_wait_for_interrupt()
471 return -ETIMEDOUT; in rspi_wait_for_interrupt()
490 dev_err(&rspi->ctlr->dev, "transmit timeout\n"); in rspi_data_out()
504 dev_err(&rspi->ctlr->dev, "receive timeout\n"); in rspi_data_in()
511 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx, in rspi_pio_transfer() argument
514 while (n-- > 0) { in rspi_pio_transfer()
515 if (tx) { in rspi_pio_transfer()
516 int ret = rspi_data_out(rspi, *tx++); in rspi_pio_transfer()
535 rspi->dma_callbacked = 1; in rspi_dma_complete()
536 wake_up_interruptible(&rspi->wait); in rspi_dma_complete()
539 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx, in rspi_dma_transfer() argument
550 desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl, in rspi_dma_transfer()
551 rx->nents, DMA_DEV_TO_MEM, in rspi_dma_transfer()
554 ret = -EAGAIN; in rspi_dma_transfer()
558 desc_rx->callback = rspi_dma_complete; in rspi_dma_transfer()
559 desc_rx->callback_param = rspi; in rspi_dma_transfer()
569 if (tx) { in rspi_dma_transfer()
570 desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl, in rspi_dma_transfer()
571 tx->nents, DMA_MEM_TO_DEV, in rspi_dma_transfer()
574 ret = -EAGAIN; in rspi_dma_transfer()
580 desc_tx->callback = NULL; in rspi_dma_transfer()
582 desc_tx->callback = rspi_dma_complete; in rspi_dma_transfer()
583 desc_tx->callback_param = rspi; in rspi_dma_transfer()
598 if (tx) in rspi_dma_transfer()
599 disable_irq(other_irq = rspi->tx_irq); in rspi_dma_transfer()
600 if (rx && rspi->rx_irq != other_irq) in rspi_dma_transfer()
601 disable_irq(rspi->rx_irq); in rspi_dma_transfer()
604 rspi->dma_callbacked = 0; in rspi_dma_transfer()
608 dma_async_issue_pending(rspi->ctlr->dma_rx); in rspi_dma_transfer()
609 if (tx) in rspi_dma_transfer()
610 dma_async_issue_pending(rspi->ctlr->dma_tx); in rspi_dma_transfer()
612 ret = wait_event_interruptible_timeout(rspi->wait, in rspi_dma_transfer()
613 rspi->dma_callbacked, HZ); in rspi_dma_transfer()
614 if (ret > 0 && rspi->dma_callbacked) { in rspi_dma_transfer()
616 if (tx) in rspi_dma_transfer()
617 dmaengine_synchronize(rspi->ctlr->dma_tx); in rspi_dma_transfer()
619 dmaengine_synchronize(rspi->ctlr->dma_rx); in rspi_dma_transfer()
622 dev_err(&rspi->ctlr->dev, "DMA timeout\n"); in rspi_dma_transfer()
623 ret = -ETIMEDOUT; in rspi_dma_transfer()
625 if (tx) in rspi_dma_transfer()
626 dmaengine_terminate_sync(rspi->ctlr->dma_tx); in rspi_dma_transfer()
628 dmaengine_terminate_sync(rspi->ctlr->dma_rx); in rspi_dma_transfer()
633 if (tx) in rspi_dma_transfer()
634 enable_irq(rspi->tx_irq); in rspi_dma_transfer()
635 if (rx && rspi->rx_irq != other_irq) in rspi_dma_transfer()
636 enable_irq(rspi->rx_irq); in rspi_dma_transfer()
642 dmaengine_terminate_sync(rspi->ctlr->dma_rx); in rspi_dma_transfer()
644 if (ret == -EAGAIN) { in rspi_dma_transfer()
645 dev_warn_once(&rspi->ctlr->dev, in rspi_dma_transfer()
684 return xfer->len > rspi->ops->fifo_size; in __rspi_can_dma()
698 if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer)) in rspi_dma_check_then_transfer()
699 return -EAGAIN; in rspi_dma_check_then_transfer()
701 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */ in rspi_dma_check_then_transfer()
702 return rspi_dma_transfer(rspi, &xfer->tx_sg, in rspi_dma_check_then_transfer()
703 xfer->rx_buf ? &xfer->rx_sg : NULL); in rspi_dma_check_then_transfer()
711 xfer->effective_speed_hz = rspi->speed_hz; in rspi_common_transfer()
714 if (ret != -EAGAIN) in rspi_common_transfer()
717 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len); in rspi_common_transfer()
734 if (xfer->rx_buf) { in rspi_transfer_one()
756 static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx, in qspi_trigger_transfer_out_in() argument
767 dev_err(&rspi->ctlr->dev, "transmit timeout\n"); in qspi_trigger_transfer_out_in()
771 rspi_write_data(rspi, *tx++); in qspi_trigger_transfer_out_in()
775 dev_err(&rspi->ctlr->dev, "receive timeout\n"); in qspi_trigger_transfer_out_in()
781 len -= n; in qspi_trigger_transfer_out_in()
795 if (ret != -EAGAIN) in qspi_transfer_out_in()
798 return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf, in qspi_transfer_out_in()
799 xfer->rx_buf, xfer->len); in qspi_transfer_out_in()
804 const u8 *tx = xfer->tx_buf; in qspi_transfer_out() local
805 unsigned int n = xfer->len; in qspi_transfer_out()
809 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) { in qspi_transfer_out()
810 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL); in qspi_transfer_out()
811 if (ret != -EAGAIN) in qspi_transfer_out()
819 dev_err(&rspi->ctlr->dev, "transmit timeout\n"); in qspi_transfer_out()
823 rspi_write_data(rspi, *tx++); in qspi_transfer_out()
825 n -= len; in qspi_transfer_out()
836 u8 *rx = xfer->rx_buf; in qspi_transfer_in()
837 unsigned int n = xfer->len; in qspi_transfer_in()
841 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) { in qspi_transfer_in()
842 ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg); in qspi_transfer_in()
843 if (ret != -EAGAIN) in qspi_transfer_in()
851 dev_err(&rspi->ctlr->dev, "receive timeout\n"); in qspi_transfer_in()
857 n -= len; in qspi_transfer_in()
868 xfer->effective_speed_hz = rspi->speed_hz; in qspi_transfer_one()
869 if (spi->mode & SPI_LOOP) { in qspi_transfer_one()
871 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) { in qspi_transfer_one()
874 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) { in qspi_transfer_one()
885 if (xfer->tx_buf) in qspi_transfer_mode()
886 switch (xfer->tx_nbits) { in qspi_transfer_mode()
894 if (xfer->rx_buf) in qspi_transfer_mode()
895 switch (xfer->rx_nbits) { in qspi_transfer_mode()
912 u16 current_mode = 0xffff, mode; in qspi_setup_sequencer() local
914 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in qspi_setup_sequencer()
915 mode = qspi_transfer_mode(xfer); in qspi_setup_sequencer()
916 if (mode == current_mode) { in qspi_setup_sequencer()
917 len += xfer->len; in qspi_setup_sequencer()
921 /* Transfer mode change */ in qspi_setup_sequencer()
924 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); in qspi_setup_sequencer()
928 dev_err(&msg->spi->dev, in qspi_setup_sequencer()
930 return -EINVAL; in qspi_setup_sequencer()
933 /* Program transfer mode for this transfer */ in qspi_setup_sequencer()
934 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i)); in qspi_setup_sequencer()
935 current_mode = mode; in qspi_setup_sequencer()
936 len = xfer->len; in qspi_setup_sequencer()
941 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); in qspi_setup_sequencer()
942 rspi_write8(rspi, i - 1, RSPI_SPSCR); in qspi_setup_sequencer()
950 struct rspi_data *rspi = spi_controller_get_devdata(spi->controller); in rspi_setup()
953 if (spi->cs_gpiod) in rspi_setup()
956 pm_runtime_get_sync(&rspi->pdev->dev); in rspi_setup()
957 spin_lock_irq(&rspi->lock); in rspi_setup()
960 if (spi->mode & SPI_CS_HIGH) in rspi_setup()
961 sslp |= SSLP_SSLP(spi->chip_select); in rspi_setup()
963 sslp &= ~SSLP_SSLP(spi->chip_select); in rspi_setup()
966 spin_unlock_irq(&rspi->lock); in rspi_setup()
967 pm_runtime_put(&rspi->pdev->dev); in rspi_setup()
975 struct spi_device *spi = msg->spi; in rspi_prepare_message()
989 rspi->speed_hz = spi->max_speed_hz; in rspi_prepare_message()
990 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in rspi_prepare_message()
991 if (xfer->speed_hz < rspi->speed_hz) in rspi_prepare_message()
992 rspi->speed_hz = xfer->speed_hz; in rspi_prepare_message()
995 rspi->spcmd = SPCMD_SSLKP; in rspi_prepare_message()
996 if (spi->mode & SPI_CPOL) in rspi_prepare_message()
997 rspi->spcmd |= SPCMD_CPOL; in rspi_prepare_message()
998 if (spi->mode & SPI_CPHA) in rspi_prepare_message()
999 rspi->spcmd |= SPCMD_CPHA; in rspi_prepare_message()
1000 if (spi->mode & SPI_LSB_FIRST) in rspi_prepare_message()
1001 rspi->spcmd |= SPCMD_LSBF; in rspi_prepare_message()
1004 rspi->spcmd |= SPCMD_SSLA(spi->cs_gpiod ? rspi->ctlr->unused_native_cs in rspi_prepare_message()
1005 : spi->chip_select); in rspi_prepare_message()
1007 /* CMOS output mode and MOSI signal from previous transfer */ in rspi_prepare_message()
1008 rspi->sppcr = 0; in rspi_prepare_message()
1009 if (spi->mode & SPI_LOOP) in rspi_prepare_message()
1010 rspi->sppcr |= SPPCR_SPLP; in rspi_prepare_message()
1012 rspi->ops->set_config_register(rspi, 8); in rspi_prepare_message()
1014 if (msg->spi->mode & in rspi_prepare_message()
1022 /* Enable SPI function in master mode */ in rspi_prepare_message()
1036 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); in rspi_unprepare_message()
1048 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); in rspi_irq_mux()
1057 wake_up(&rspi->wait); in rspi_irq_mux()
1068 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); in rspi_irq_rx()
1071 wake_up(&rspi->wait); in rspi_irq_rx()
1083 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); in rspi_irq_tx()
1086 wake_up(&rspi->wait); in rspi_irq_tx()
1108 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); in rspi_request_dma_chan()
1137 if (dev->of_node) { in rspi_request_dma()
1141 } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) { in rspi_request_dma()
1142 dma_tx_id = rspi_pd->dma_tx_id; in rspi_request_dma()
1143 dma_rx_id = rspi_pd->dma_rx_id; in rspi_request_dma()
1149 ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id, in rspi_request_dma()
1150 res->start); in rspi_request_dma()
1151 if (!ctlr->dma_tx) in rspi_request_dma()
1152 return -ENODEV; in rspi_request_dma()
1154 ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id, in rspi_request_dma()
1155 res->start); in rspi_request_dma()
1156 if (!ctlr->dma_rx) { in rspi_request_dma()
1157 dma_release_channel(ctlr->dma_tx); in rspi_request_dma()
1158 ctlr->dma_tx = NULL; in rspi_request_dma()
1159 return -ENODEV; in rspi_request_dma()
1162 ctlr->can_dma = rspi_can_dma; in rspi_request_dma()
1169 if (ctlr->dma_tx) in rspi_release_dma()
1170 dma_release_channel(ctlr->dma_tx); in rspi_release_dma()
1171 if (ctlr->dma_rx) in rspi_release_dma()
1172 dma_release_channel(ctlr->dma_rx); in rspi_release_dma()
1179 rspi_release_dma(rspi->ctlr); in rspi_remove()
1180 pm_runtime_disable(&pdev->dev); in rspi_remove()
1201 .fifo_size = 8, /* 8 for TX, 32 for RX */
1222 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1223 /* QSPI on R-Car Gen2 */
1242 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs); in rspi_parse_dt()
1244 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error); in rspi_parse_dt()
1248 ctlr->num_chipselect = num_cs; in rspi_parse_dt()
1273 return -EINVAL; in rspi_parse_dt()
1284 return -ENOMEM; in rspi_request_irq()
1299 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); in rspi_probe()
1301 return -ENOMEM; in rspi_probe()
1303 ops = of_device_get_match_data(&pdev->dev); in rspi_probe()
1305 ret = rspi_parse_dt(&pdev->dev, ctlr); in rspi_probe()
1309 ops = (struct spi_ops *)pdev->id_entry->driver_data; in rspi_probe()
1310 rspi_pd = dev_get_platdata(&pdev->dev); in rspi_probe()
1311 if (rspi_pd && rspi_pd->num_chipselect) in rspi_probe()
1312 ctlr->num_chipselect = rspi_pd->num_chipselect; in rspi_probe()
1314 ctlr->num_chipselect = 2; /* default */ in rspi_probe()
1319 rspi->ops = ops; in rspi_probe()
1320 rspi->ctlr = ctlr; in rspi_probe()
1323 rspi->addr = devm_ioremap_resource(&pdev->dev, res); in rspi_probe()
1324 if (IS_ERR(rspi->addr)) { in rspi_probe()
1325 ret = PTR_ERR(rspi->addr); in rspi_probe()
1329 rspi->clk = devm_clk_get(&pdev->dev, NULL); in rspi_probe()
1330 if (IS_ERR(rspi->clk)) { in rspi_probe()
1331 dev_err(&pdev->dev, "cannot get clock\n"); in rspi_probe()
1332 ret = PTR_ERR(rspi->clk); in rspi_probe()
1336 rspi->pdev = pdev; in rspi_probe()
1337 pm_runtime_enable(&pdev->dev); in rspi_probe()
1339 init_waitqueue_head(&rspi->wait); in rspi_probe()
1340 spin_lock_init(&rspi->lock); in rspi_probe()
1342 ctlr->bus_num = pdev->id; in rspi_probe()
1343 ctlr->setup = rspi_setup; in rspi_probe()
1344 ctlr->auto_runtime_pm = true; in rspi_probe()
1345 ctlr->transfer_one = ops->transfer_one; in rspi_probe()
1346 ctlr->prepare_message = rspi_prepare_message; in rspi_probe()
1347 ctlr->unprepare_message = rspi_unprepare_message; in rspi_probe()
1348 ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | in rspi_probe()
1349 SPI_LOOP | ops->extra_mode_bits; in rspi_probe()
1350 clksrc = clk_get_rate(rspi->clk); in rspi_probe()
1351 ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, ops->max_div); in rspi_probe()
1352 ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, ops->min_div); in rspi_probe()
1353 ctlr->flags = ops->flags; in rspi_probe()
1354 ctlr->dev.of_node = pdev->dev.of_node; in rspi_probe()
1355 ctlr->use_gpio_descriptors = true; in rspi_probe()
1356 ctlr->max_native_cs = rspi->ops->num_hw_ss; in rspi_probe()
1364 rspi->rx_irq = rspi->tx_irq = ret; in rspi_probe()
1366 rspi->rx_irq = ret; in rspi_probe()
1367 ret = platform_get_irq_byname(pdev, "tx"); in rspi_probe()
1369 rspi->tx_irq = ret; in rspi_probe()
1372 if (rspi->rx_irq == rspi->tx_irq) { in rspi_probe()
1374 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux, in rspi_probe()
1377 /* Multi-interrupt mode, only SPRI and SPTI are used */ in rspi_probe()
1378 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx, in rspi_probe()
1381 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq, in rspi_probe()
1382 rspi_irq_tx, "tx", rspi); in rspi_probe()
1385 dev_err(&pdev->dev, "request_irq error\n"); in rspi_probe()
1389 ret = rspi_request_dma(&pdev->dev, ctlr, res); in rspi_probe()
1391 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); in rspi_probe()
1393 ret = devm_spi_register_controller(&pdev->dev, ctlr); in rspi_probe()
1395 dev_err(&pdev->dev, "devm_spi_register_controller error.\n"); in rspi_probe()
1399 dev_info(&pdev->dev, "probed\n"); in rspi_probe()
1406 pm_runtime_disable(&pdev->dev); in rspi_probe()
1425 return spi_controller_suspend(rspi->ctlr); in rspi_suspend()
1432 return spi_controller_resume(rspi->ctlr); in rspi_resume()