Lines Matching +full:tx +full:- +full:output +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
58 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
64 #define TxINT_ENAB 0x2 /* Tx Int Enable */
83 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
85 #define ENT_HM 0x10 /* Enter Hunt Mode */
105 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
106 #define EXTSYNC 0x30 /* External Sync Mode */
108 #define X1CLK 0x0 /* x1 clock mode */
109 #define X16CLK 0x40 /* x16 clock mode */
110 #define X32CLK 0x80 /* x32 clock mode */
111 #define X64CLK 0xC0 /* x64 clock mode */
116 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
119 #define TxENAB 0x8 /* Tx Enable */
121 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
122 #define Tx7 0x20 /* Tx 7 bits/character */
123 #define Tx6 0x40 /* Tx 6 bits/character */
124 #define Tx8 0x60 /* Tx 8 bits/character */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
133 #define AUTO_TxFLAG 1 /* Automatic Tx SDLC Flag */
157 #define LOOPMODE 2 /* SDLC Loop mode */
161 #define NRZ 0 /* NRZ mode */
162 #define NRZI 0x20 /* NRZI mode */
167 /* Write Register 11 (Clock Mode control) */
168 #define TRxCXT 0 /* TRxC = Xtal output */
170 #define TRxCBR 2 /* TRxC = BR Generator Output */
171 #define TRxCDP 3 /* TRxC = DPLL output */
175 #define TCBR 0x10 /* Transmit clock = BR Generator output */
176 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
179 #define RCBR 0x40 /* Receive clock = BR Generator output */
180 #define RCDPLL 0x60 /* Receive clock = DPLL output */
193 #define SEARCH 0x20 /* Enter search mode */
198 #define SFMM 0xc0 /* Set FM mode */
199 #define SNRZI 0xe0 /* Set NRZI mode */
208 #define TxUIE 0x40 /* Tx Underrun/EOM IE */
215 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
219 #define TxEOM 0x40 /* Tx underrun */
239 /* Read Register 2 (channel b only) - Interrupt vector */
252 #define CHBTxIP 0x2 /* Channel B Tx IP */
255 #define CHATxIP 0x10 /* Channel A Tx IP */
277 #define ZS_CLEARERR(channel) do { sbus_writeb(ERR_RES, &channel->control); \
280 #define ZS_CLEARSTAT(channel) do { sbus_writeb(RES_EXT_INT, &channel->control); \
283 #define ZS_CLEARFIFO(channel) do { sbus_readb(&channel->data); \
285 sbus_readb(&channel->data); \
287 sbus_readb(&channel->data); \