Lines Matching +full:tx +full:- +full:output +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0 */
29 int tx_stopped; /* Output is suspended. */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
87 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
92 #define TxINT_ENAB 0x2 /* Tx Int Enable */
110 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
112 #define ENT_HM 0x10 /* Enter Hunt Mode */
132 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
133 #define EXTSYNC 0x30 /* External Sync Mode */
135 #define X1CLK 0x0 /* x1 clock mode */
136 #define X16CLK 0x40 /* x16 clock mode */
137 #define X32CLK 0x80 /* x32 clock mode */
138 #define X64CLK 0xc0 /* x64 clock mode */
142 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
144 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
145 #define TxENAB 0x8 /* Tx Enable */
147 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
148 #define Tx7 0x20 /* Tx 7 bits/character */
149 #define Tx6 0x40 /* Tx 6 bits/character */
150 #define Tx8 0x60 /* Tx 8 bits/character */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
174 #define LOOPMODE 2 /* SDLC Loop mode */
178 #define NRZ 0 /* NRZ mode */
179 #define NRZI 0x20 /* NRZI mode */
184 /* Write Register 11 (Clock Mode Control) */
185 #define TRxCXT 0 /* TRxC = Xtal output */
187 #define TRxCBR 2 /* TRxC = BR Generator Output */
188 #define TRxCDP 3 /* TRxC = DPLL output */
192 #define TCBR 0x10 /* Transmit clock = BR Generator output */
193 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
196 #define RCBR 0x40 /* Receive clock = BR Generator output */
197 #define RCDPLL 0x60 /* Receive clock = DPLL output */
210 #define SEARCH 0x20 /* Enter search mode */
215 #define SFMM 0xc0 /* Set FM mode */
216 #define SNRZI 0xe0 /* Set NRZI mode */
224 #define TxUIE 0x40 /* Tx Underrun/EOM IE */
231 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
235 #define TxEOM 0x40 /* Tx underrun */
255 /* Read Register 2 (Interrupt Vector (WR2) -- channel A). */
257 /* Read Register 2 (Modified Interrupt Vector -- channel B). */
259 /* Read Register 3 (Interrupt Pending Bits -- channel A only). */
261 #define CHBTxIP 0x2 /* Channel B Tx IP */
264 #define CHATxIP 0x10 /* Channel A Tx IP */