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/Linux-v5.10/drivers/pci/controller/dwc/
Dpcie-tegra194.c3 * PCIe host controller driver for Tegra194 SoC
33 #include "pcie-designware.h"
319 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value, in appl_writel() argument
322 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
325 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg) in appl_readl() argument
327 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
337 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); in apply_bad_link_workaround() local
346 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
350 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
351 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); in apply_bad_link_workaround()
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DKconfig23 bool "TI DRA7xx PCIe controller Host Mode"
31 Enables support for the PCIe controller in the DRA7xx SoC to work in
32 host mode. There are two instances of PCIe controller in DRA7xx.
39 bool "TI DRA7xx PCIe controller Endpoint Mode"
46 Enables support for the PCIe controller in the DRA7xx SoC to work in
47 endpoint mode. There are two instances of PCIe controller in DRA7xx.
57 bool "Platform bus based DesignWare PCIe Controller - Host mode"
62 Enables support for the PCIe controller in the Designware IP to
63 work in host mode. There are two instances of PCIe controller in
71 bool "Platform bus based DesignWare PCIe Controller - Endpoint mode"
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Dpci-layerscape.c3 * PCIe host controller driver for Freescale Layerscape SoCs
23 #include "pcie-designware.h"
56 static bool ls_pcie_is_bridge(struct ls_pcie *pcie) in ls_pcie_is_bridge() argument
58 struct dw_pcie *pci = pcie->pci; in ls_pcie_is_bridge()
68 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) in ls_pcie_clear_multifunction() argument
70 struct dw_pcie *pci = pcie->pci; in ls_pcie_clear_multifunction()
76 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) in ls_pcie_drop_msg_tlp() argument
79 struct dw_pcie *pci = pcie->pci; in ls_pcie_drop_msg_tlp()
86 static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie) in ls_pcie_disable_outbound_atus() argument
91 dw_pcie_disable_atu(pcie->pci, i, DW_PCIE_REGION_OUTBOUND); in ls_pcie_disable_outbound_atus()
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Dpcie-qcom.c3 * Qualcomm PCIe root complex driver
31 #include "pcie-designware.h"
176 int (*get_resources)(struct qcom_pcie *pcie);
177 int (*init)(struct qcom_pcie *pcie);
178 int (*post_init)(struct qcom_pcie *pcie);
179 void (*deinit)(struct qcom_pcie *pcie);
180 void (*post_deinit)(struct qcom_pcie *pcie);
181 void (*ltssm_enable)(struct qcom_pcie *pcie);
196 static void qcom_ep_reset_assert(struct qcom_pcie *pcie) in qcom_ep_reset_assert() argument
198 gpiod_set_value_cansleep(pcie->reset, 1); in qcom_ep_reset_assert()
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Dpcie-armada8k.c3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
26 #include "pcie-designware.h"
74 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_disable_phys() argument
79 phy_power_off(pcie->phy[i]); in armada8k_pcie_disable_phys()
80 phy_exit(pcie->phy[i]); in armada8k_pcie_disable_phys()
84 static int armada8k_pcie_enable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_enable_phys() argument
90 ret = phy_init(pcie->phy[i]); in armada8k_pcie_enable_phys()
94 ret = phy_set_mode_ext(pcie->phy[i], PHY_MODE_PCIE, in armada8k_pcie_enable_phys()
95 pcie->phy_count); in armada8k_pcie_enable_phys()
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/Linux-v5.10/drivers/pci/controller/
Dpci-aardvark.c3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
30 /* PCIe core registers */
128 /* PCIe core controller registers */
136 /* PCIe Central Interrupts Registers */
205 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
207 writel(val, pcie->base + reg); in advk_writel()
210 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
212 return readl(pcie->base + reg); in advk_readl()
215 static inline u16 advk_read16(struct advk_pcie *pcie, u64 reg) in advk_read16() argument
217 return advk_readl(pcie, (reg & ~0x3)) >> ((reg & 0x3) * 8); in advk_read16()
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Dpcie-altera.c6 * Description: Altera PCIe host controller driver
45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
60 #define TLP_CFG_DW0(pcie, cfg) \ argument
63 #define TLP_CFG_DW1(pcie, tag, be) \ argument
64 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
99 int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
100 void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
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Dpci-tegra.c3 * PCIe host controller driver for Tegra SoCs
8 * Based on NVIDIA PCIe driver
11 * Bits taken from arch/arm/mach-dove/pcie.c
271 * entries, one entry per PCIe port. These field definitions and desired
376 struct tegra_pcie *pcie; member
394 static inline void afi_writel(struct tegra_pcie *pcie, u32 value, in afi_writel() argument
397 writel(value, pcie->afi + offset); in afi_writel()
400 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset) in afi_readl() argument
402 return readl(pcie->afi + offset); in afi_readl()
405 static inline void pads_writel(struct tegra_pcie *pcie, u32 value, in pads_writel() argument
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Dpcie-xilinx-nwl.c3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
160 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
174 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) in nwl_bridge_readl() argument
176 return readl(pcie->breg_base + off); in nwl_bridge_readl()
179 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() argument
181 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
184 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) in nwl_pcie_link_up() argument
186 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
191 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument
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Dpcie-iproc.c24 #include "pcie-iproc.h"
99 * iProc PCIe outbound mapping controller specific parameters
146 * iProc PCIe inbound mapping type
160 * iProc PCIe inbound mapping controller specific parameters
232 * iProc PCIe host registers
309 /* iProc PCIe PAXB BCMA registers */
320 /* iProc PCIe PAXB registers */
336 /* iProc PCIe PAXB v2 registers */
365 /* iProc PCIe PAXC v1 registers */
374 /* iProc PCIe PAXC v2 registers */
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Dpcie-brcmstb.c37 /* Broadcom STB PCIe Register Offsets */
144 /* PCIe parameters */
175 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) argument
176 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) argument
177 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) argument
191 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val);
192 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val);
193 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val);
194 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val);
216 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
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Dpcie-rcar-host.c3 * PCIe driver for Renesas R-Car SoCs
7 * arch/sh/drivers/pci/pcie-sh7786.c
33 #include "pcie-rcar.h"
50 /* Structure representing the PCIe interface */
52 struct rcar_pcie pcie; member
61 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) in rcar_read_conf() argument
64 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_read_conf()
74 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_config_access() local
102 *data = rcar_pci_read_reg(pcie, PCICONF(index)); in rcar_pcie_config_access()
104 rcar_pci_write_reg(pcie, *data, PCICONF(index)); in rcar_pcie_config_access()
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Dpcie-rcar-ep.c3 * PCIe endpoint driver for Renesas R-Car SoCs
20 #include "pcie-rcar.h"
24 /* Structure representing the PCIe interface */
26 struct rcar_pcie pcie; member
36 static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie) in rcar_pcie_ep_hw_init() argument
40 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_ep_hw_init()
43 rcar_pci_write_reg(pcie, 0, PCIEMSR); in rcar_pcie_ep_hw_init()
46 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); in rcar_pcie_ep_hw_init()
47 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), in rcar_pcie_ep_hw_init()
49 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f, in rcar_pcie_ep_hw_init()
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Dpcie-iproc-platform.c20 #include "pcie-iproc.h"
24 .compatible = "brcm,iproc-pcie",
27 .compatible = "brcm,iproc-pcie-paxb-v2",
30 .compatible = "brcm,iproc-pcie-paxc",
33 .compatible = "brcm,iproc-pcie-paxc-v2",
43 struct iproc_pcie *pcie; in iproc_pcie_pltfm_probe() local
49 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in iproc_pcie_pltfm_probe()
53 pcie = pci_host_bridge_priv(bridge); in iproc_pcie_pltfm_probe()
55 pcie->dev = dev; in iproc_pcie_pltfm_probe()
56 pcie->type = (enum iproc_pcie_type) of_device_get_match_data(dev); in iproc_pcie_pltfm_probe()
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DKconfig7 bool "Marvell EBU PCIe controller"
15 tristate "Aardvark PCIe controller"
21 Add support for Aardvark 64bit PCIe Host Controller. This
26 bool "NWL PCIe Core"
31 NWL PCIe controller. The controller can act as Root Port
41 bool "NVIDIA Tegra PCIe controller"
46 Say Y here if you want support for the PCIe host controller found
59 bool "Renesas R-Car PCIe controller"
64 Say Y here if you want PCIe controller support on R-Car SoCs.
68 bool "Renesas R-Car PCIe host controller"
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Dpcie-tango.c28 struct tango_pcie *pcie = irq_desc_get_handler_data(desc); in tango_msi_isr() local
32 spin_lock(&pcie->used_msi_lock); in tango_msi_isr()
34 while ((pos = find_next_bit(pcie->used_msi, MSI_MAX, pos)) < MSI_MAX) { in tango_msi_isr()
36 status = readl_relaxed(pcie->base + SMP8759_STATUS + base / 8); in tango_msi_isr()
38 virq = irq_find_mapping(pcie->dom, base + idx); in tango_msi_isr()
44 spin_unlock(&pcie->used_msi_lock); in tango_msi_isr()
50 struct tango_pcie *pcie = d->chip_data; in tango_ack() local
54 writel_relaxed(bit, pcie->base + SMP8759_STATUS + offset); in tango_ack()
60 struct tango_pcie *pcie = d->chip_data; in update_msi_enable() local
65 spin_lock_irqsave(&pcie->used_msi_lock, flags); in update_msi_enable()
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/Linux-v5.10/drivers/staging/mt7621-pci/
Dpci-mt7621.c12 * support RT2880/RT3883 PCIe
15 * support RT6855/MT7620 PCIe
66 /* PCIe RC control registers */
92 * struct mt7621_pcie_port - PCIe port information
95 * @pcie: pointer to PCIe host info
106 struct mt7621_pcie *pcie; member
116 * struct mt7621_pcie - PCIe host information
122 * @dev: Pointer to PCIe device
124 * @ports: pointer to PCIe port information
125 * @irq_map: irq mapping info according pcie link status
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/Linux-v5.10/drivers/pci/controller/mobiveil/
Dpcie-mobiveil-host.c3 * PCIe host controller driver for Mobiveil PCIe Host controller
28 #include "pcie-mobiveil.h"
53 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
54 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
62 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
74 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus()
88 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local
89 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
90 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
105 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
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Dpcie-layerscape-gen4.c3 * PCIe Gen4 host controller driver for NXP Layerscape SoCs
23 #include "pcie-mobiveil.h"
45 static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off) in ls_pcie_g4_lut_readl() argument
47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_LUT_OFF + off); in ls_pcie_g4_lut_readl()
50 static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie, in ls_pcie_g4_lut_writel() argument
53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_LUT_OFF + off); in ls_pcie_g4_lut_writel()
56 static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off) in ls_pcie_g4_pf_readl() argument
58 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_pcie_g4_pf_readl()
61 static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie, in ls_pcie_g4_pf_writel() argument
64 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_pcie_g4_pf_writel()
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Dpcie-mobiveil.c3 * PCIe host controller driver for Mobiveil PCIe Host controller
18 #include "pcie-mobiveil.h"
28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
48 mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off)); in mobiveil_pcie_comp_addr()
49 return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off); in mobiveil_pcie_comp_addr()
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/Linux-v5.10/drivers/pci/controller/cadence/
Dpcie-cadence.c3 // Cadence PCIe controller driver.
8 #include "pcie-cadence.h"
10 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, in cdns_pcie_set_outbound_region() argument
30 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0); in cdns_pcie_set_outbound_region()
31 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), addr1); in cdns_pcie_set_outbound_region()
33 /* Set the PCIe header descriptor */ in cdns_pcie_set_outbound_region()
42 * PCIe descriptor, the PCI function number must be set into in cdns_pcie_set_outbound_region()
46 * mode, the PCIe controller may support more than one function. This in cdns_pcie_set_outbound_region()
47 * function number needs to be set properly into the outbound PCIe in cdns_pcie_set_outbound_region()
56 * the PCIe controller will use the captured values for the bus and in cdns_pcie_set_outbound_region()
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Dpci-j721e.c3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
22 #include "pcie-cadence.h"
68 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_user_readl() argument
70 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()
73 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_user_writel() argument
76 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()
79 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_intd_readl() argument
81 return readl(pcie->intd_cfg_base + offset); in j721e_pcie_intd_readl()
84 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_intd_writel() argument
87 writel(value, pcie->intd_cfg_base + offset); in j721e_pcie_intd_writel()
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Dpcie-cadence-ep.c3 // Cadence PCIe endpoint controller driver.
13 #include "pcie-cadence.h"
23 struct cdns_pcie *pcie = &ep->pcie; in cdns_pcie_ep_write_header() local
25 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); in cdns_pcie_ep_write_header()
26 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); in cdns_pcie_ep_write_header()
27 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); in cdns_pcie_ep_write_header()
28 cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, in cdns_pcie_ep_write_header()
30 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE, in cdns_pcie_ep_write_header()
32 cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id); in cdns_pcie_ep_write_header()
33 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin); in cdns_pcie_ep_write_header()
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/Linux-v5.10/Documentation/devicetree/bindings/pci/
Drcar-pci.txt1 * Renesas R-Car PCIe interface
4 compatible: "renesas,pcie-r8a7742" for the R8A7742 SoC;
5 "renesas,pcie-r8a7743" for the R8A7743 SoC;
6 "renesas,pcie-r8a7744" for the R8A7744 SoC;
7 "renesas,pcie-r8a774a1" for the R8A774A1 SoC;
8 "renesas,pcie-r8a774b1" for the R8A774B1 SoC;
9 "renesas,pcie-r8a774c0" for the R8A774C0 SoC;
10 "renesas,pcie-r8a7779" for the R8A7779 SoC;
11 "renesas,pcie-r8a7790" for the R8A7790 SoC;
12 "renesas,pcie-r8a7791" for the R8A7791 SoC;
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Dlayerscape-pci.txt1 Freescale Layerscape PCIe controller
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
10 register available in the Freescale PCIe controller register set,
11 which can allow determining the underlying DesignWare PCIe controller version
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
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