3  * PCIe Gen4 host controller driver for NXP Layerscape SoCs
23 #include "pcie-mobiveil.h"
45 static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off)  in ls_pcie_g4_lut_readl()  argument
47 	return ioread32(pcie->pci.csr_axi_slave_base + PCIE_LUT_OFF + off);  in ls_pcie_g4_lut_readl()
50 static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie,  in ls_pcie_g4_lut_writel()  argument
53 	iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_LUT_OFF + off);  in ls_pcie_g4_lut_writel()
56 static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off)  in ls_pcie_g4_pf_readl()  argument
58 	return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off);  in ls_pcie_g4_pf_readl()
61 static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie,  in ls_pcie_g4_pf_writel()  argument
64 	iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off);  in ls_pcie_g4_pf_writel()
69 	struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);  in ls_pcie_g4_link_up()  local
72 	state = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);  in ls_pcie_g4_link_up()
81 static void ls_pcie_g4_disable_interrupt(struct ls_pcie_g4 *pcie)  in ls_pcie_g4_disable_interrupt()  argument
83 	struct mobiveil_pcie *mv_pci = &pcie->pci;  in ls_pcie_g4_disable_interrupt()
88 static void ls_pcie_g4_enable_interrupt(struct ls_pcie_g4 *pcie)  in ls_pcie_g4_enable_interrupt()  argument
90 	struct mobiveil_pcie *mv_pci = &pcie->pci;  in ls_pcie_g4_enable_interrupt()
101 static int ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie)  in ls_pcie_g4_reinit_hw()  argument
103 	struct mobiveil_pcie *mv_pci = &pcie->pci;  in ls_pcie_g4_reinit_hw()
111 		val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_INT_STAT);  in ls_pcie_g4_reinit_hw()
120 	val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);  in ls_pcie_g4_reinit_hw()
122 	ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);  in ls_pcie_g4_reinit_hw()
124 	val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);  in ls_pcie_g4_reinit_hw()
126 	ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);  in ls_pcie_g4_reinit_hw()
128 	val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);  in ls_pcie_g4_reinit_hw()
130 	ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);  in ls_pcie_g4_reinit_hw()
138 		dev_err(dev, "PCIe link training timeout\n");  in ls_pcie_g4_reinit_hw()
147 	struct ls_pcie_g4 *pcie = (struct ls_pcie_g4 *)dev_id;  in ls_pcie_g4_isr()  local
148 	struct mobiveil_pcie *mv_pci = &pcie->pci;  in ls_pcie_g4_isr()
156 		ls_pcie_g4_disable_interrupt(pcie);  in ls_pcie_g4_isr()
157 		schedule_delayed_work(&pcie->dwork, msecs_to_jiffies(1));  in ls_pcie_g4_isr()
167 	struct ls_pcie_g4 *pcie = to_ls_pcie_g4(mv_pci);  in ls_pcie_g4_interrupt_init()  local
172 	pcie->irq = platform_get_irq_byname(pdev, "intr");  in ls_pcie_g4_interrupt_init()
173 	if (pcie->irq < 0)  in ls_pcie_g4_interrupt_init()
174 		return pcie->irq;  in ls_pcie_g4_interrupt_init()
176 	ret = devm_request_irq(dev, pcie->irq, ls_pcie_g4_isr,  in ls_pcie_g4_interrupt_init()
177 			       IRQF_SHARED, pdev->name, pcie);  in ls_pcie_g4_interrupt_init()
179 		dev_err(dev, "Can't register PCIe IRQ, errno = %d\n", ret);  in ls_pcie_g4_interrupt_init()
190 	struct ls_pcie_g4 *pcie = container_of(dwork, struct ls_pcie_g4, dwork);  in ls_pcie_g4_reset()  local
191 	struct mobiveil_pcie *mv_pci = &pcie->pci;  in ls_pcie_g4_reset()
198 	if (!ls_pcie_g4_reinit_hw(pcie))  in ls_pcie_g4_reset()
201 	ls_pcie_g4_enable_interrupt(pcie);  in ls_pcie_g4_reset()
217 	struct ls_pcie_g4 *pcie;  in ls_pcie_g4_probe()  local
226 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));  in ls_pcie_g4_probe()
230 	pcie = pci_host_bridge_priv(bridge);  in ls_pcie_g4_probe()
231 	mv_pci = &pcie->pci;  in ls_pcie_g4_probe()
238 	platform_set_drvdata(pdev, pcie);  in ls_pcie_g4_probe()
240 	INIT_DELAYED_WORK(&pcie->dwork, ls_pcie_g4_reset);  in ls_pcie_g4_probe()
248 	ls_pcie_g4_enable_interrupt(pcie);  in ls_pcie_g4_probe()
254 	{ .compatible = "fsl,lx2160a-pcie", },
260 		.name = "layerscape-pcie-gen4",