1 // SPDX-License-Identifier: GPL-2.0
2 /**
3  * pci-j721e - PCIe controller driver for TI's J721E SoCs
4  *
5  * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
6  * Author: Kishon Vijay Abraham I <kishon@ti.com>
7  */
8 
9 #include <linux/delay.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/io.h>
12 #include <linux/irqchip/chained_irq.h>
13 #include <linux/irqdomain.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/of_device.h>
16 #include <linux/of_irq.h>
17 #include <linux/pci.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 
21 #include "../../pci.h"
22 #include "pcie-cadence.h"
23 
24 #define ENABLE_REG_SYS_2	0x108
25 #define STATUS_REG_SYS_2	0x508
26 #define STATUS_CLR_REG_SYS_2	0x708
27 #define LINK_DOWN		BIT(1)
28 
29 #define J721E_PCIE_USER_CMD_STATUS	0x4
30 #define LINK_TRAINING_ENABLE		BIT(0)
31 
32 #define J721E_PCIE_USER_LINKSTATUS	0x14
33 #define LINK_STATUS			GENMASK(1, 0)
34 
35 enum link_status {
36 	NO_RECEIVERS_DETECTED,
37 	LINK_TRAINING_IN_PROGRESS,
38 	LINK_UP_DL_IN_PROGRESS,
39 	LINK_UP_DL_COMPLETED,
40 };
41 
42 #define J721E_MODE_RC			BIT(7)
43 #define LANE_COUNT_MASK			BIT(8)
44 #define LANE_COUNT(n)			((n) << 8)
45 
46 #define GENERATION_SEL_MASK		GENMASK(1, 0)
47 
48 #define MAX_LANES			2
49 
50 struct j721e_pcie {
51 	struct device		*dev;
52 	u32			mode;
53 	u32			num_lanes;
54 	struct cdns_pcie	*cdns_pcie;
55 	void __iomem		*user_cfg_base;
56 	void __iomem		*intd_cfg_base;
57 };
58 
59 enum j721e_pcie_mode {
60 	PCI_MODE_RC,
61 	PCI_MODE_EP,
62 };
63 
64 struct j721e_pcie_data {
65 	enum j721e_pcie_mode	mode;
66 };
67 
j721e_pcie_user_readl(struct j721e_pcie * pcie,u32 offset)68 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
69 {
70 	return readl(pcie->user_cfg_base + offset);
71 }
72 
j721e_pcie_user_writel(struct j721e_pcie * pcie,u32 offset,u32 value)73 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset,
74 					  u32 value)
75 {
76 	writel(value, pcie->user_cfg_base + offset);
77 }
78 
j721e_pcie_intd_readl(struct j721e_pcie * pcie,u32 offset)79 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset)
80 {
81 	return readl(pcie->intd_cfg_base + offset);
82 }
83 
j721e_pcie_intd_writel(struct j721e_pcie * pcie,u32 offset,u32 value)84 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset,
85 					  u32 value)
86 {
87 	writel(value, pcie->intd_cfg_base + offset);
88 }
89 
j721e_pcie_link_irq_handler(int irq,void * priv)90 static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
91 {
92 	struct j721e_pcie *pcie = priv;
93 	struct device *dev = pcie->dev;
94 	u32 reg;
95 
96 	reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2);
97 	if (!(reg & LINK_DOWN))
98 		return IRQ_NONE;
99 
100 	dev_err(dev, "LINK DOWN!\n");
101 
102 	j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, LINK_DOWN);
103 	return IRQ_HANDLED;
104 }
105 
j721e_pcie_config_link_irq(struct j721e_pcie * pcie)106 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
107 {
108 	u32 reg;
109 
110 	reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2);
111 	reg |= LINK_DOWN;
112 	j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg);
113 }
114 
j721e_pcie_start_link(struct cdns_pcie * cdns_pcie)115 static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie)
116 {
117 	struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
118 	u32 reg;
119 
120 	reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
121 	reg |= LINK_TRAINING_ENABLE;
122 	j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
123 
124 	return 0;
125 }
126 
j721e_pcie_stop_link(struct cdns_pcie * cdns_pcie)127 static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie)
128 {
129 	struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
130 	u32 reg;
131 
132 	reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
133 	reg &= ~LINK_TRAINING_ENABLE;
134 	j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
135 }
136 
j721e_pcie_link_up(struct cdns_pcie * cdns_pcie)137 static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie)
138 {
139 	struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
140 	u32 reg;
141 
142 	reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS);
143 	reg &= LINK_STATUS;
144 	if (reg == LINK_UP_DL_COMPLETED)
145 		return true;
146 
147 	return false;
148 }
149 
150 static const struct cdns_pcie_ops j721e_pcie_ops = {
151 	.start_link = j721e_pcie_start_link,
152 	.stop_link = j721e_pcie_stop_link,
153 	.link_up = j721e_pcie_link_up,
154 };
155 
j721e_pcie_set_mode(struct j721e_pcie * pcie,struct regmap * syscon)156 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon)
157 {
158 	struct device *dev = pcie->dev;
159 	u32 mask = J721E_MODE_RC;
160 	u32 mode = pcie->mode;
161 	u32 val = 0;
162 	int ret = 0;
163 
164 	if (mode == PCI_MODE_RC)
165 		val = J721E_MODE_RC;
166 
167 	ret = regmap_update_bits(syscon, 0, mask, val);
168 	if (ret)
169 		dev_err(dev, "failed to set pcie mode\n");
170 
171 	return ret;
172 }
173 
j721e_pcie_set_link_speed(struct j721e_pcie * pcie,struct regmap * syscon)174 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
175 				     struct regmap *syscon)
176 {
177 	struct device *dev = pcie->dev;
178 	struct device_node *np = dev->of_node;
179 	int link_speed;
180 	u32 val = 0;
181 	int ret;
182 
183 	link_speed = of_pci_get_max_link_speed(np);
184 	if (link_speed < 2)
185 		link_speed = 2;
186 
187 	val = link_speed - 1;
188 	ret = regmap_update_bits(syscon, 0, GENERATION_SEL_MASK, val);
189 	if (ret)
190 		dev_err(dev, "failed to set link speed\n");
191 
192 	return ret;
193 }
194 
j721e_pcie_set_lane_count(struct j721e_pcie * pcie,struct regmap * syscon)195 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
196 				     struct regmap *syscon)
197 {
198 	struct device *dev = pcie->dev;
199 	u32 lanes = pcie->num_lanes;
200 	u32 val = 0;
201 	int ret;
202 
203 	val = LANE_COUNT(lanes - 1);
204 	ret = regmap_update_bits(syscon, 0, LANE_COUNT_MASK, val);
205 	if (ret)
206 		dev_err(dev, "failed to set link count\n");
207 
208 	return ret;
209 }
210 
j721e_pcie_ctrl_init(struct j721e_pcie * pcie)211 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
212 {
213 	struct device *dev = pcie->dev;
214 	struct device_node *node = dev->of_node;
215 	struct regmap *syscon;
216 	int ret;
217 
218 	syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl");
219 	if (IS_ERR(syscon)) {
220 		dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n");
221 		return PTR_ERR(syscon);
222 	}
223 
224 	ret = j721e_pcie_set_mode(pcie, syscon);
225 	if (ret < 0) {
226 		dev_err(dev, "Failed to set pci mode\n");
227 		return ret;
228 	}
229 
230 	ret = j721e_pcie_set_link_speed(pcie, syscon);
231 	if (ret < 0) {
232 		dev_err(dev, "Failed to set link speed\n");
233 		return ret;
234 	}
235 
236 	ret = j721e_pcie_set_lane_count(pcie, syscon);
237 	if (ret < 0) {
238 		dev_err(dev, "Failed to set num-lanes\n");
239 		return ret;
240 	}
241 
242 	return 0;
243 }
244 
cdns_ti_pcie_config_read(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * value)245 static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
246 				    int where, int size, u32 *value)
247 {
248 	if (pci_is_root_bus(bus))
249 		return pci_generic_config_read32(bus, devfn, where, size,
250 						 value);
251 
252 	return pci_generic_config_read(bus, devfn, where, size, value);
253 }
254 
cdns_ti_pcie_config_write(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 value)255 static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
256 				     int where, int size, u32 value)
257 {
258 	if (pci_is_root_bus(bus))
259 		return pci_generic_config_write32(bus, devfn, where, size,
260 						  value);
261 
262 	return pci_generic_config_write(bus, devfn, where, size, value);
263 }
264 
265 static struct pci_ops cdns_ti_pcie_host_ops = {
266 	.map_bus	= cdns_pci_map_bus,
267 	.read		= cdns_ti_pcie_config_read,
268 	.write		= cdns_ti_pcie_config_write,
269 };
270 
271 static const struct j721e_pcie_data j721e_pcie_rc_data = {
272 	.mode = PCI_MODE_RC,
273 };
274 
275 static const struct j721e_pcie_data j721e_pcie_ep_data = {
276 	.mode = PCI_MODE_EP,
277 };
278 
279 static const struct of_device_id of_j721e_pcie_match[] = {
280 	{
281 		.compatible = "ti,j721e-pcie-host",
282 		.data = &j721e_pcie_rc_data,
283 	},
284 	{
285 		.compatible = "ti,j721e-pcie-ep",
286 		.data = &j721e_pcie_ep_data,
287 	},
288 	{},
289 };
290 
j721e_pcie_probe(struct platform_device * pdev)291 static int j721e_pcie_probe(struct platform_device *pdev)
292 {
293 	struct device *dev = &pdev->dev;
294 	struct device_node *node = dev->of_node;
295 	struct pci_host_bridge *bridge;
296 	struct j721e_pcie_data *data;
297 	struct cdns_pcie *cdns_pcie;
298 	struct j721e_pcie *pcie;
299 	struct cdns_pcie_rc *rc;
300 	struct cdns_pcie_ep *ep;
301 	struct gpio_desc *gpiod;
302 	void __iomem *base;
303 	u32 num_lanes;
304 	u32 mode;
305 	int ret;
306 	int irq;
307 
308 	data = (struct j721e_pcie_data *)of_device_get_match_data(dev);
309 	if (!data)
310 		return -EINVAL;
311 
312 	mode = (u32)data->mode;
313 
314 	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
315 	if (!pcie)
316 		return -ENOMEM;
317 
318 	pcie->dev = dev;
319 	pcie->mode = mode;
320 
321 	base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg");
322 	if (IS_ERR(base))
323 		return PTR_ERR(base);
324 	pcie->intd_cfg_base = base;
325 
326 	base = devm_platform_ioremap_resource_byname(pdev, "user_cfg");
327 	if (IS_ERR(base))
328 		return PTR_ERR(base);
329 	pcie->user_cfg_base = base;
330 
331 	ret = of_property_read_u32(node, "num-lanes", &num_lanes);
332 	if (ret || num_lanes > MAX_LANES)
333 		num_lanes = 1;
334 	pcie->num_lanes = num_lanes;
335 
336 	if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
337 		return -EINVAL;
338 
339 	irq = platform_get_irq_byname(pdev, "link_state");
340 	if (irq < 0)
341 		return irq;
342 
343 	dev_set_drvdata(dev, pcie);
344 	pm_runtime_enable(dev);
345 	ret = pm_runtime_get_sync(dev);
346 	if (ret < 0) {
347 		dev_err(dev, "pm_runtime_get_sync failed\n");
348 		goto err_get_sync;
349 	}
350 
351 	ret = j721e_pcie_ctrl_init(pcie);
352 	if (ret < 0) {
353 		dev_err(dev, "pm_runtime_get_sync failed\n");
354 		goto err_get_sync;
355 	}
356 
357 	ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0,
358 			       "j721e-pcie-link-down-irq", pcie);
359 	if (ret < 0) {
360 		dev_err(dev, "failed to request link state IRQ %d\n", irq);
361 		goto err_get_sync;
362 	}
363 
364 	j721e_pcie_config_link_irq(pcie);
365 
366 	switch (mode) {
367 	case PCI_MODE_RC:
368 		if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) {
369 			ret = -ENODEV;
370 			goto err_get_sync;
371 		}
372 
373 		bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
374 		if (!bridge) {
375 			ret = -ENOMEM;
376 			goto err_get_sync;
377 		}
378 
379 		bridge->ops = &cdns_ti_pcie_host_ops;
380 		rc = pci_host_bridge_priv(bridge);
381 
382 		cdns_pcie = &rc->pcie;
383 		cdns_pcie->dev = dev;
384 		cdns_pcie->ops = &j721e_pcie_ops;
385 		pcie->cdns_pcie = cdns_pcie;
386 
387 		gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
388 		if (IS_ERR(gpiod)) {
389 			ret = PTR_ERR(gpiod);
390 			if (ret != -EPROBE_DEFER)
391 				dev_err(dev, "Failed to get reset GPIO\n");
392 			goto err_get_sync;
393 		}
394 
395 		ret = cdns_pcie_init_phy(dev, cdns_pcie);
396 		if (ret) {
397 			dev_err(dev, "Failed to init phy\n");
398 			goto err_get_sync;
399 		}
400 
401 		/*
402 		 * "Power Sequencing and Reset Signal Timings" table in
403 		 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
404 		 * indicates PERST# should be deasserted after minimum of 100us
405 		 * once REFCLK is stable. The REFCLK to the connector in RC
406 		 * mode is selected while enabling the PHY. So deassert PERST#
407 		 * after 100 us.
408 		 */
409 		if (gpiod) {
410 			usleep_range(100, 200);
411 			gpiod_set_value_cansleep(gpiod, 1);
412 		}
413 
414 		ret = cdns_pcie_host_setup(rc);
415 		if (ret < 0)
416 			goto err_pcie_setup;
417 
418 		break;
419 	case PCI_MODE_EP:
420 		if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP)) {
421 			ret = -ENODEV;
422 			goto err_get_sync;
423 		}
424 
425 		ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
426 		if (!ep) {
427 			ret = -ENOMEM;
428 			goto err_get_sync;
429 		}
430 
431 		cdns_pcie = &ep->pcie;
432 		cdns_pcie->dev = dev;
433 		cdns_pcie->ops = &j721e_pcie_ops;
434 		pcie->cdns_pcie = cdns_pcie;
435 
436 		ret = cdns_pcie_init_phy(dev, cdns_pcie);
437 		if (ret) {
438 			dev_err(dev, "Failed to init phy\n");
439 			goto err_get_sync;
440 		}
441 
442 		ret = cdns_pcie_ep_setup(ep);
443 		if (ret < 0)
444 			goto err_pcie_setup;
445 
446 		break;
447 	default:
448 		dev_err(dev, "INVALID device type %d\n", mode);
449 	}
450 
451 	return 0;
452 
453 err_pcie_setup:
454 	cdns_pcie_disable_phy(cdns_pcie);
455 
456 err_get_sync:
457 	pm_runtime_put(dev);
458 	pm_runtime_disable(dev);
459 
460 	return ret;
461 }
462 
j721e_pcie_remove(struct platform_device * pdev)463 static int j721e_pcie_remove(struct platform_device *pdev)
464 {
465 	struct j721e_pcie *pcie = platform_get_drvdata(pdev);
466 	struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
467 	struct device *dev = &pdev->dev;
468 
469 	cdns_pcie_disable_phy(cdns_pcie);
470 	pm_runtime_put(dev);
471 	pm_runtime_disable(dev);
472 
473 	return 0;
474 }
475 
476 static struct platform_driver j721e_pcie_driver = {
477 	.probe  = j721e_pcie_probe,
478 	.remove = j721e_pcie_remove,
479 	.driver = {
480 		.name	= "j721e-pcie",
481 		.of_match_table = of_j721e_pcie_match,
482 		.suppress_bind_attrs = true,
483 	},
484 };
485 builtin_platform_driver(j721e_pcie_driver);
486