Lines Matching full:pcie
37 /* Broadcom STB PCIe Register Offsets */
144 /* PCIe parameters */
175 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) argument
176 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) argument
177 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) argument
191 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val);
192 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val);
193 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val);
194 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val);
216 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
217 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
272 /* Internal PCIe Host Controller Information.*/
288 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
289 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
366 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) in brcm_pcie_set_ssc() argument
372 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
377 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
384 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
390 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
402 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) in brcm_pcie_set_gen() argument
404 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
405 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
408 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
411 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
414 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, in brcm_pcie_set_outbound_win() argument
424 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); in brcm_pcie_set_outbound_win()
425 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); in brcm_pcie_set_outbound_win()
431 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
436 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
443 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
446 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
449 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
452 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
456 .name = "BRCM STB PCIe MSI",
603 static void brcm_msi_remove(struct brcm_pcie *pcie) in brcm_msi_remove() argument
605 struct brcm_msi *msi = pcie->msi; in brcm_msi_remove()
634 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) in brcm_pcie_enable_msi() argument
638 struct device *dev = pcie->dev; in brcm_pcie_enable_msi()
652 msi->base = pcie->base; in brcm_pcie_enable_msi()
653 msi->np = pcie->np; in brcm_pcie_enable_msi()
654 msi->target_addr = pcie->msi_target_addr; in brcm_pcie_enable_msi()
656 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; in brcm_pcie_enable_msi()
675 pcie->msi = msi; in brcm_pcie_enable_msi()
681 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) in brcm_pcie_rc_mode() argument
683 void __iomem *base = pcie->base; in brcm_pcie_rc_mode()
689 static bool brcm_pcie_link_up(struct brcm_pcie *pcie) in brcm_pcie_link_up() argument
691 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); in brcm_pcie_link_up()
710 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_map_conf() local
711 void __iomem *base = pcie->base; in brcm_pcie_map_conf()
720 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); in brcm_pcie_map_conf()
730 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_generic() argument
735 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
737 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
740 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_7278() argument
745 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
747 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
750 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_7278() argument
755 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
757 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
760 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_generic() argument
764 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
766 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
769 static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, in brcm_pcie_get_rc_bar2_size_and_offset() argument
773 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_get_rc_bar2_size_and_offset()
775 struct device *dev = pcie->dev; in brcm_pcie_get_rc_bar2_size_and_offset()
793 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, in brcm_pcie_get_rc_bar2_size_and_offset()
798 pcie->num_memc = 1; in brcm_pcie_get_rc_bar2_size_and_offset()
799 pcie->memc_size[0] = 1ULL << fls64(size - 1); in brcm_pcie_get_rc_bar2_size_and_offset()
801 pcie->num_memc = ret; in brcm_pcie_get_rc_bar2_size_and_offset()
805 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_rc_bar2_size_and_offset()
806 size += pcie->memc_size[i]; in brcm_pcie_get_rc_bar2_size_and_offset()
808 /* System memory starts at this address in PCIe-space */ in brcm_pcie_get_rc_bar2_size_and_offset()
818 * PCIe controller integration, which prohibits any access above the in brcm_pcie_get_rc_bar2_size_and_offset()
823 * The PCIe host controller by design must set the inbound viewport to in brcm_pcie_get_rc_bar2_size_and_offset()
826 * matters, the viewport must start on a pcie-address that is aligned in brcm_pcie_get_rc_bar2_size_and_offset()
837 * region in the first 4GB of pcie-space, as some legacy devices can in brcm_pcie_get_rc_bar2_size_and_offset()
856 static int brcm_pcie_setup(struct brcm_pcie *pcie) in brcm_pcie_setup() argument
858 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_setup()
860 void __iomem *base = pcie->base; in brcm_pcie_setup()
861 struct device *dev = pcie->dev; in brcm_pcie_setup()
871 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_setup()
875 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
888 if (pcie->type == BCM2711) in brcm_pcie_setup()
890 else if (pcie->type == BCM7278) in brcm_pcie_setup()
901 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size, in brcm_pcie_setup()
914 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
915 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; in brcm_pcie_setup()
934 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; in brcm_pcie_setup()
936 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; in brcm_pcie_setup()
938 /* disable the PCIe->GISB memory window (RC_BAR1) */ in brcm_pcie_setup()
943 /* disable the PCIe->SCB memory window (RC_BAR3) */ in brcm_pcie_setup()
948 if (pcie->gen) in brcm_pcie_setup()
949 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_setup()
952 pcie->perst_set(pcie, 0); in brcm_pcie_setup()
958 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) in brcm_pcie_setup()
961 if (!brcm_pcie_link_up(pcie)) { in brcm_pcie_setup()
966 if (!brcm_pcie_rc_mode(pcie)) { in brcm_pcie_setup()
967 dev_err(dev, "PCIe misconfigured; is in EP mode\n"); in brcm_pcie_setup()
978 dev_err(pcie->dev, "too many outbound wins\n"); in brcm_pcie_setup()
982 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, in brcm_pcie_setup()
990 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
999 * a PCIe-PCIe bridge (the default setting is to be EP mode). in brcm_pcie_setup()
1006 if (pcie->ssc) { in brcm_pcie_setup()
1007 ret = brcm_pcie_set_ssc(pcie); in brcm_pcie_setup()
1021 /* PCIe->SCB endian mode for BAR */ in brcm_pcie_setup()
1038 /* L23 is a low-power PCIe link state */
1039 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie) in brcm_pcie_enter_l23() argument
1041 void __iomem *base = pcie->base; in brcm_pcie_enter_l23()
1061 dev_err(pcie->dev, "failed to enter low-power link state\n"); in brcm_pcie_enter_l23()
1064 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) in brcm_phy_cntl() argument
1078 void __iomem *base = pcie->base; in brcm_phy_cntl()
1095 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); in brcm_phy_cntl()
1100 static inline int brcm_phy_start(struct brcm_pcie *pcie) in brcm_phy_start() argument
1102 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1105 static inline int brcm_phy_stop(struct brcm_pcie *pcie) in brcm_phy_stop() argument
1107 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1110 static void brcm_pcie_turn_off(struct brcm_pcie *pcie) in brcm_pcie_turn_off() argument
1112 void __iomem *base = pcie->base; in brcm_pcie_turn_off()
1115 if (brcm_pcie_link_up(pcie)) in brcm_pcie_turn_off()
1116 brcm_pcie_enter_l23(pcie); in brcm_pcie_turn_off()
1118 pcie->perst_set(pcie, 1); in brcm_pcie_turn_off()
1130 /* Shutdown PCIe bridge */ in brcm_pcie_turn_off()
1131 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_turn_off()
1136 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_suspend() local
1139 brcm_pcie_turn_off(pcie); in brcm_pcie_suspend()
1140 ret = brcm_phy_stop(pcie); in brcm_pcie_suspend()
1141 clk_disable_unprepare(pcie->clk); in brcm_pcie_suspend()
1148 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_resume() local
1153 base = pcie->base; in brcm_pcie_resume()
1154 clk_prepare_enable(pcie->clk); in brcm_pcie_resume()
1156 ret = brcm_phy_start(pcie); in brcm_pcie_resume()
1161 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume()
1171 ret = brcm_pcie_setup(pcie); in brcm_pcie_resume()
1175 if (pcie->msi) in brcm_pcie_resume()
1176 brcm_msi_set_regs(pcie->msi); in brcm_pcie_resume()
1181 clk_disable_unprepare(pcie->clk); in brcm_pcie_resume()
1185 static void __brcm_pcie_remove(struct brcm_pcie *pcie) in __brcm_pcie_remove() argument
1187 brcm_msi_remove(pcie); in __brcm_pcie_remove()
1188 brcm_pcie_turn_off(pcie); in __brcm_pcie_remove()
1189 brcm_phy_stop(pcie); in __brcm_pcie_remove()
1190 reset_control_assert(pcie->rescal); in __brcm_pcie_remove()
1191 clk_disable_unprepare(pcie->clk); in __brcm_pcie_remove()
1196 struct brcm_pcie *pcie = platform_get_drvdata(pdev); in brcm_pcie_remove() local
1197 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_remove()
1201 __brcm_pcie_remove(pcie); in brcm_pcie_remove()
1207 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1208 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1209 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1210 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1211 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1220 struct brcm_pcie *pcie; in brcm_pcie_probe() local
1223 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); in brcm_pcie_probe()
1233 pcie = pci_host_bridge_priv(bridge); in brcm_pcie_probe()
1234 pcie->dev = &pdev->dev; in brcm_pcie_probe()
1235 pcie->np = np; in brcm_pcie_probe()
1236 pcie->reg_offsets = data->offsets; in brcm_pcie_probe()
1237 pcie->type = data->type; in brcm_pcie_probe()
1238 pcie->perst_set = data->perst_set; in brcm_pcie_probe()
1239 pcie->bridge_sw_init_set = data->bridge_sw_init_set; in brcm_pcie_probe()
1241 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1242 if (IS_ERR(pcie->base)) in brcm_pcie_probe()
1243 return PTR_ERR(pcie->base); in brcm_pcie_probe()
1245 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); in brcm_pcie_probe()
1246 if (IS_ERR(pcie->clk)) in brcm_pcie_probe()
1247 return PTR_ERR(pcie->clk); in brcm_pcie_probe()
1250 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1252 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
1254 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_probe()
1259 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); in brcm_pcie_probe()
1260 if (IS_ERR(pcie->rescal)) { in brcm_pcie_probe()
1261 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1262 return PTR_ERR(pcie->rescal); in brcm_pcie_probe()
1265 ret = reset_control_deassert(pcie->rescal); in brcm_pcie_probe()
1269 ret = brcm_phy_start(pcie); in brcm_pcie_probe()
1271 reset_control_assert(pcie->rescal); in brcm_pcie_probe()
1272 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1276 ret = brcm_pcie_setup(pcie); in brcm_pcie_probe()
1280 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); in brcm_pcie_probe()
1282 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1283 if (pci_msi_enabled() && msi_np == pcie->np) { in brcm_pcie_probe()
1284 ret = brcm_pcie_enable_msi(pcie); in brcm_pcie_probe()
1286 dev_err(pcie->dev, "probe of internal MSI failed"); in brcm_pcie_probe()
1292 bridge->sysdata = pcie; in brcm_pcie_probe()
1294 platform_set_drvdata(pdev, pcie); in brcm_pcie_probe()
1298 __brcm_pcie_remove(pcie); in brcm_pcie_probe()
1313 .name = "brcm-pcie",
1321 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");