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/Linux-v5.10/drivers/clk/sprd/
Dsc9860-clk.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
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/Linux-v5.10/drivers/clk/sunxi-ng/
Dccu-sun4i-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
26 #include "ccu-sun4i-a10.h"
32 .m = _SUNXI_CCU_DIV(0, 2),
36 .hw.init = CLK_HW_INIT("pll-core",
48 * With sigma-delta modulation for fractional-N on the audio PLL,
58 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
59 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
65 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
71 .hw.init = CLK_HW_INIT("pll-audio-base",
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Dccu-sun5i.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun5i.h"
30 .m = _SUNXI_CCU_DIV(0, 2),
34 .hw.init = CLK_HW_INIT("pll-core",
46 * With sigma-delta modulation for fractional-N on the audio PLL,
56 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
57 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
68 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
74 .hw.init = CLK_HW_INIT("pll-audio-base",
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Dccu-suniv-f1c100s.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
24 #include "ccu-suniv-f1c100s.h"
32 .m = _SUNXI_CCU_DIV(0, 2),
38 .hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
54 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
57 0, 5, /* M */
62 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
65 0, 4, /* M */
74 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
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Dccu-sun50i-h6-r.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
18 #include "ccu-sun50i-h6-r.h"
21 * Information about AR100 and AHB/APB clocks in R_CCU are gathered from
26 "iosc", "pll-periph0" };
52 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
54 static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
70 .hw.init = CLK_HW_INIT_PARENTS("r-apb2",
84 static SUNXI_CCU_GATE(r_apb1_timer_clk, "r-apb1-timer", "r-apb1",
86 static SUNXI_CCU_GATE(r_apb1_twd_clk, "r-apb1-twd", "r-apb1",
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Dccu-sun50i-a100-r.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
19 #include "ccu-sun50i-a100-r.h"
22 "iosc", "pll-periph0" };
48 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &r_cpus_clk.common.hw, 1, 1, 0);
55 .hw.init = CLK_HW_INIT("r-apb1",
56 "r-ahb",
76 .hw.init = CLK_HW_INIT_PARENTS("r-apb2",
91 static SUNXI_CCU_GATE_DATA(r_apb1_timer_clk, "r-apb1-timer", clk_parent_r_apb1,
94 static SUNXI_CCU_GATE_DATA(r_apb1_twd_clk, "r-apb1-twd", clk_parent_r_apb1,
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/Linux-v5.10/Documentation/devicetree/bindings/arm/stm32/
Dst,mlahb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: STMicroelectronics STM32 ML-AHB interconnect bindings
10 - Fabien Dessenne <fabien.dessenne@st.com>
11 - Arnaud Pouliquen <arnaud.pouliquen@st.com>
14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
23 - $ref: /schemas/simple-bus.yaml#
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/Linux-v5.10/Documentation/devicetree/bindings/soc/qcom/
Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Mukesh Savaliya <msavaliy@codeaurora.org>
11 - Akash Asthana <akashast@codeaurora.org>
24 - qcom,geni-se-qup
30 clock-names:
32 - const: m-ahb
33 - const: s-ahb
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/Linux-v5.10/drivers/clk/sunxi/
Dclk-sun9i-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2014 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
9 #include <linux/clk-provider.h>
14 #include "clk-factors.h"
18 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
20 * rate = (parent_rate * n >> p) / (m + 1);
23 * p and m are named div1 and div2 in Allwinner's SDK
29 int m = 1; in sun9i_a80_get_pll4_factors() local
33 n = DIV_ROUND_UP(req->rate, 6000000); in sun9i_a80_get_pll4_factors()
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Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
29 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
37 /* Normalize value to a 6M multiple */ in sun4i_get_pll1_factors()
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
41 /* m is always zero for pll1 */ in sun4i_get_pll1_factors()
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/Linux-v5.10/drivers/clk/
Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
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Dclk-ast2600.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #define pr_fmt(fmt) "clk-ast2600: " fmt
14 #include <dt-bindings/clock/ast2600-clock.h>
16 #include "clk-aspeed.h"
62 [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
63 [ASPEED_CLK_GATE_ECLK] = { 1, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
64 [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
65 /* vclk parent - dclk/d1clk/hclk/mclk */
66 [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
67 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
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/Linux-v5.10/drivers/clk/imx/
Dclk-imx27.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/clk-provider.h>
9 #include <dt-bindings/clock/imx27-clock.h>
41 "ahb", "ipg", "per1_div", "per2_div",
43 "nfc_div", "mshc_div", "vpu_div", "60m",
81 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); in _mx27_clocks_init()
82 clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in _mx27_clocks_init()
84 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); in _mx27_clocks_init()
85 clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); in _mx27_clocks_init()
88 clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); in _mx27_clocks_init()
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Dclk-imx6sx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <linux/clk-provider.h>
37 static const char *pcie_axi_sels[] = { "axi", "ahb", };
61 "lcdif1_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
138 clk_hw_data->num = IMX6SX_CLK_CLK_END; in imx6sx_clocks_init()
139 hws = clk_hw_data->hws; in imx6sx_clocks_init()
154 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); in imx6sx_clocks_init()
185 clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk); in imx6sx_clocks_init()
186 clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk); in imx6sx_clocks_init()
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/Linux-v5.10/arch/arm/mach-ep93xx/include/mach/
Dep93xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
13 * fe800000 5M per-platform mappings
14 * fed00000 80800000 2M APB
15 * fef00000 80000000 1M AHB
/Linux-v5.10/drivers/pci/controller/
Dpci-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * pci-rcar-gen2: internal PCI bus support
26 /* AHB-PCI Bridge PCI communication registers */
108 struct rcar_pci_priv *priv = bus->sysdata; in rcar_pci_cfg_base()
114 /* Only one EHCI/OHCI device built-in */ in rcar_pci_cfg_base()
126 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG); in rcar_pci_cfg_base()
127 return priv->reg + (slot >> 1) * 0x100 + where; in rcar_pci_cfg_base()
136 struct device *dev = priv->dev; in rcar_pci_err_irq()
137 u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG); in rcar_pci_err_irq()
144 priv->reg + RCAR_PCI_INT_STATUS_REG); in rcar_pci_err_irq()
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/Linux-v5.10/arch/arm/boot/dts/
Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
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Dusb_a9260.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * usb_a9260.dts - Device Tree file for Caloa USB A9260 board
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 /dts-v1/;
13 compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9";
16 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
23 ahb {
26 atmel,wakeup-counter = <10>;
27 atmel,wakeup-rtt-timer;
Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
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Dtny_a9260_common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs";
19 clock-frequency = <32768>;
23 clock-frequency = <12000000>;
27 ahb {
31 compatible = "atmel,tcb-timer";
36 compatible = "atmel,tcb-timer";
49 nand_controller: nand-controller {
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/Linux-v5.10/arch/mips/ath25/
Dar5312.c9 * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
65 pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", in ar5312_ahb_err_handler()
68 machine_restart("AHB error"); /* Catastrophic failure */ in ar5312_ahb_err_handler()
97 ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq)); in ar5312_misc_irq_unmask()
103 ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0); in ar5312_misc_irq_mask()
108 .name = "ar5312-misc",
153 if (request_irq(irq, ar5312_ahb_err_handler, 0, "ar5312-ahb-error", in ar5312_arch_init_irq()
155 pr_err("Failed to register ar5312-ahb-error interrupt\n"); in ar5312_arch_init_irq()
169 .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
174 .name = "physmap-flash",
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/Linux-v5.10/drivers/net/wireless/ath/ath5k/
DKconfig1 # SPDX-License-Identifier: ISC
22 If you choose to build a module, it'll be called ath5k. Say M if
34 mount -t debugfs debug /sys/kernel/debug
56 bool "Atheros 5xxx AHB bus support"
73 This enables non-standard IEEE 802.11 channels on ath5k, which
/Linux-v5.10/drivers/staging/media/sunxi/cedrus/
Dcedrus_hw.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
11 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
13 * Marek Szyprowski, <m.szyprowski@samsung.com>
19 #include <linux/dma-mapping.h>
27 #include <media/videobuf2-core.h>
28 #include <media/v4l2-mem2mem.h>
39 * FIXME: This is only valid on 32-bits DDR's, we should test in cedrus_engine_enable()
59 return -EINVAL; in cedrus_engine_enable()
62 if (ctx->src_fmt.width == 4096) in cedrus_engine_enable()
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/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dste-u300-syscon-clock.txt1 Clock bindings for ST-Ericsson U300 System Controller Clocks
6 - compatible: must be "stericsson,u300-syscon-clk"
7 - #clock-cells: must be <0>
8 - clock-type: specifies the type of clock:
12 - clock-id: specifies the clock in the type range
15 - clocks: parent clock(s)
20 -------------------
40 2 10 AHB Subsystem Bridge clock
45 gpio_clk: gpio_clk@13M {
46 #clock-cells = <0>;
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/Linux-v5.10/drivers/soc/lantiq/
Dfpi-bus.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2011-2015 John Crispin <blogic@phrozen.org>
6 * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
29 struct device *dev = &pdev->dev; in ltq_fpi_probe()
30 struct device_node *np = dev->of_node; in ltq_fpi_probe()
45 ret = device_property_read_u32(dev, "lantiq,offset-endianness", in ltq_fpi_probe()
48 dev_err(&pdev->dev, "Failed to get RCU reg offset\n"); in ltq_fpi_probe()
55 dev_warn(&pdev->dev, in ltq_fpi_probe()
56 "Failed to configure RCU AHB endianness\n"); in ltq_fpi_probe()
63 return of_platform_populate(dev->of_node, NULL, NULL, dev); in ltq_fpi_probe()
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